US10164912B2
Methods and apparatus for Ethernet auto-negotiation (AN) with parallel detect for 10G DAC or other non-auto-negotiated modes. AN base pages are transmitted from an Ethernet apparatus to advertise the ability to support at least one Institute of Electrical and Electronics Engineers (IEEE) 802.3 Ethernet specification supporting AN. A receiver and associated processing circuitry is configured to perform two detection modes in parallel, including a first detection mode that looks for a valid signal transmitted from an Ethernet link peer that does not support AN and a second detection mode looking for AN pages from an IEEE 802.3 Ethernet link peer that supports AN. If the link peer does not support AN, an Ethernet link is set up to use signaling in accordance with the Ethernet specification that does not support AN. If the link peer supports AN, an Ethernet link is set up using a corresponding IEEE 802.3 Ethernet link supporting AN. Supported non-AN Ethernet links include 10G DAC links.
US10164902B2
The present disclosure relates to allocating a resource in a cloud computing system to a task using multiple cloud application programming interface (API) keys that allow an access to the cloud computing system. An allocation method includes receiving a request for a task from the client terminal, determining a resource amount necessary for the task, selecting multiple cloud API keys for allocation of the determined resource amount, requesting resource allocation corresponding to the determined resource amount to the cloud computing system using the selected multiple cloud API keys, and being allocated with a resource in the cloud computing system, and executing the task requested from the client terminal using the allocated cloud resource.
US10164894B2
Some embodiments provide a novel network control system that provides publications for managing different slices (e.g., logical and/or physical entities) of a network. The publications are published from publisher controllers in the network control system to subscriber controllers. The network control system uses publications with generation numbers and buffered subscribers to implement the fixed points in order to help maintain a consistent network state. Buffered subscribers buffer the inputs received from a publisher in case the publisher becomes unavailable. Rather than deleting all of the output state that is based on the published inputs, the buffered subscriber allows the subscriber to maintain the network state until an explicit change to the state is received at the subscriber from a publisher (e.g., a restarted publisher, a backup publisher, etc.).
US10164888B2
Disclosed herein is a computing device with a USB port configured to implement Quality of Service (QoS) associated with a network. The computing device includes a modem to enable each of the IP applications to communicate with a network via one or more bearer channels. At least one of the bearer channels is managed by a set of packet filter rules corresponding to a Quality of Service (QoS) description. The computing device also includes a Universal Serial Bus (USB) interface to couple a host and the modem, the USB interface comprising a plurality of logical channels each comprising logical channel endpoints. Each logical channel endpoint is dedicated to a particular bearer channel.
US10164884B2
A search apparatus, a search configuration method, and a search method are disclosed. The search apparatus includes N pipeline stages, where each pipeline stage includes a search unit. A search unit of each pipeline stage is configured with a prefix node. A prefix node configured in the (N−1)th-stage search unit is obtained by dividing, into sub-trees. A multi-bit Trie tree formed by a search table, a prefix node configured in the (N−2)th-stage search unit is obtained by dividing, into sub-trees. A multi-bit Trie tree formed by an associated prefix of the prefix node configured in the (N−1)th-stage search unit, and prefix node configuration is performed by means of iteration for multiple times. By using the search apparatus provided in the present invention, a memory resource to be occupied and a quantity of pipeline stages can be reduced, thereby reducing a search delay and decreasing difficulties in implementation.
US10164878B2
In an aspect of the disclosure, a method, a computer-readable medium, and a computer system are provided. A first device of the computer system emulates one or more sensors monitoring one or more operating characteristics of a host of a BMC of the computer system. The first device generates first data of a first sensor of the one or more emulated sensors. The first sensor monitors a first operating characteristic of the one or more operating characteristics. The first device sends, to the BMC, the first data and an indication indicating that the first data is associated with the first sensor.
US10164872B2
A process is implemented by a network device for enabling the provisioning of explicit trees in a network by reporting link aggregation group (LAG) configuration information to a path computation element (PCE). The network device implements a LAG module and an intermediate system-intermediate system (IS-IS) module that includes an IS-IS path control and reservation module (ISIS-PCR). The process includes reporting LAG configuration by the LAG module to the IS-IS module within the network device, sending a link state protocol data unit (PDU) (LSP) with the LAG configuration in a LAG sub type length value (TLV) by the ISIS-PCR, receiving, by the IS-IS module, an explicit tree that specifies at least one virtual local area network (VLAN) identifier (VID) to an aggregation link of the LAG assignment, and translating, by the ISIS-PCR module, the explicit tree into a LAG configuration, the LAG configuration specifying a conversation to aggregation link assignment.
US10164866B2
A mechanism for multicast (M-VIM) is used to resolve address looking up problems for different types of VXLAN related overlay networks for multicast and broadcast traffics. A Multicast Overlay Ferry Proxy (MOFP) is introduced between a VXLAN domain and the CNI domain for ferrying control plane and data panel information. The M-VIM mechanism comprises three parts: a VXLAN Module; a CNI Module; and a proxy mechanism.
US10164862B2
A communication system includes: a plurality of nodes each of which forwards a packet; a terminal device to establish a connection with at least one of the nodes, and to access a network through at least one of the nodes; and a control device to control a packet forwarding route in response to a request which is sent from at least one of the nodes to request for setting the packet forwarding route. The control device includes: a unit that stores a plurality of location information respectively corresponding to the respective nodes; a unit that receives the request sent from at least one of the nodes connected to the terminal device; and a unit that identifies a location of the terminal device based on the location information corresponding to the at least one of the nodes, and controls the packet forwarding route by using the location of the terminal device.
US10164855B2
A system may be configured for: identifying a plurality of resource deficiencies associated with a first plurality of users; constructing a resource deficiency object repository comprising a plurality of resource deficiency objects associated with the plurality of resource deficiencies; determining a resource provisioning capability associated with the second user; constructing a resource provisioning object associated with the resource provisioning capability of the second user; determining that the resource provisioning capability associated with the second user matches a first resource deficiency associated with the first user; establishing, automatically, a resource connection between the first resource deficiency object and the resource provisioning object and initiating transfer of resources corresponding to the resource provisioning capability associated with the second user to the first user.
US10164854B2
Providing dynamic latency in an integration flow. An integration flow connecting multiple integration nodes and including at least one repeat node is managed, wherein a repeat node repeats by sending a message, a variation of a message, or an element of a message to multiple paths or to a single path multiple times. A repeat node is registered with a workload manager component for monitoring. Data relating to the effect on performance by the integration flow including the monitored repeat node is collected. Required latencies or variations of latencies between firing of repeats of the repeat node based on the collected data are determined. The latencies or variations of latencies between firing of the repeats of the repeat node are instructed to influence dynamically a flow of elements through the repeat node.
US10164853B2
A method for detect and mitigate anomaly in video streaming platforms is disclosed. In one embodiment, performance data from a set of workers is received at a central telemetry system (CTS), where the performance data is indicative of operational status of the set of workers. The CTS processes the performance data, including generating task-specific monitoring data based on the performance data, and it identifies whether the performance data or the task-specific monitoring data contains any anomaly. Upon an anomaly being identified, the CTS mitigates the anomaly by interacting with the set of workers.
US10164844B2
An application information acquisition unit transmits a device list of unconnected devices, which are owned devices recorded in a local storage but not retrieved by a device retrieval unit, and connected devices, which are owned devices retrieved by the device retrieval unit, to an external server via an external network. A service list display unit displays a list of device cooperation services indicated in device cooperation service list information obtained by the application information acquisition unit from the external server and a list of devices determined to be owned devices by an owned device management unit on a display unit, whereby a user is prompted to select a device cooperation service.
US10164830B2
Various embodiments manage computing networks. In one embodiment, a set of network management data associated with one or more users is analyzed. The set of network management data includes at least electronic scheduling information associated with the one or more users. A concentration of users is predicted for a given location based on the analyzing. At least one network characteristic associated with the given location is performed based on at least the predicted concentration of users.
US10164818B2
A downstream element in a pipeline processing a network flow receives a first request and executes an indexing function to compute an index into a control block for storing state information associated with the data packet. The downstream element transmits a request to an upstream element to include the index as a tag in one or more subsequent data packets that comprises the plurality of network fields and the associated values. Subsequent data packet may be received at the downstream element with the tag having the index information. The downstream element may process the subsequent data packet based on the tag without having to execute the indexing function on the subsequent data packet.
US10164806B2
A clock data recovery circuit includes; a clock recovery circuit that receives a pseudo random binary sequence (PRBS) pattern and generates a recovery clock by counting edges of the PRBS pattern, and a data recovery circuit that generates recovery data from at least one of the PRBS pattern and externally provided serial data.
US10164805B1
Various embodiments, disclosed herein, can include apparatus and methods to characterize taps of a decision feedback equalizer of a data receiver. In characterizing the taps of the decision feedback equalizer of the data receiver, a signal can be transmitted to the data receiver and the received data can be iteratively sampled at an output of the decision feedback equalizer. The sampling can include stepping a sample time relative to arrival of the received data and stepping a reference voltage level to which the received data is compared. Values of the sampled data can be compared with known correct values and such measurements can be used to characterize the taps. Additional apparatus, systems, and methods are disclosed.
US10164803B2
Disclosed are a method and an apparatus for controlling a quadrature amplitude modulation-filter bank multi-carrier (QAM-FBMC) system. A method of controlling interference is performed by a reception apparatus of the QAM-FBMC system, wherein the reception apparatus is paired with a transmission apparatus. The method includes receiving a pre-coded data symbol; and removing residual interference caused due to a non-orthogonal filter from the pre-coded data symbol by using a decision feedback equalizer.
US10164800B2
An apparatus and a method for estimation a wireless channel are disclosed. For example, the method correlates, by a correlator, a plurality of signals of a combined signal received by a receive antenna over the wireless channel from a plurality of transmit antennas, with respective DMRSs of the plurality of transmit antennas, converts, by a converter, the correlated plurality of signals from frequency to time domain, iteratively peak cancels, by a peak canceller, a largest peak of the combined impulse response and stores a scaling factor and location pair of the cancelled peak until a magnitude of a next largest peak is below a predetermined threshold, assigns, by an assigner, each of the scaling factor and location pairs to a transmit antenna, and estimates, by an estimator, for each of the plurality of transmit antennas, the wireless channel based on the assigned scaling factor and location pairs.
US10164797B2
The present invention provides a data transmission method. In the method of the present invention, a station receives an indication frame sent by an access point, where the indication frame is used for allocating a designated random contention channel; a channel state of the designated random contention channel is sensed according to the indication frame; and the station sends data on the designated random contention channel after it is detected that the designated random contention channel is in an idle state. Because in the method of the present invention, a designated random contention channel is allocated to a station, the station can send data on the designated random contention channel, contention among stations is reduced and a time for a station to be connected to a random contention channel is reduced.
US10164795B1
In some embodiments, a method includes defining, by a processor included in a first node, a virtual-extensible-local-area-network (VXLAN) tunnel between the first node included in a first layer-two network, and a second node included in a second layer-two network, the VXLAN tunnel traversing at least one node of a layer-three network. The method includes receiving, at the first node, a layer-two data unit that is sent from a third node included in the first layer-two network, to a fourth node included in the second layer-two network. The method includes encapsulating, at the first node, the layer-two data unit to define an encapsulated data unit that includes a VXLAN header. The method includes sending the encapsulated packet from the first node towards the fourth node via the VXLAN tunnel.
US10164794B2
Methods and network devices are disclosed for traversal, within a network configured for bit indexed forwarding, of a subnetwork having nodes not configured for bit indexed forwarding. In one embodiment, a method includes receiving, from a first network node not configured for bit indexed forwarding, a data message comprising a local label and a message bit array. Bit values in the message bit array identify intended destination nodes for the message. The embodiment further includes modifying the message bit array to exclude as intended destination nodes for the message any nodes not represented by one or more relative bit positions associated with the local label and stored in an ingress filter data structure. In addition, the embodiment includes forwarding a copy of the data message to a second network node, which is configured for bit indexed forwarding, identified in an accessed entry of a bit indexed forwarding table.
US10164793B2
Systems and methods for interoperating between real time networks. Systems may include a plurality of ports and switch circuitry coupled to the plurality of ports. At least one port may be coupled to a first real time network carrying first traffic. One or more other ports may be coupled to a second real time network carrying second traffic. Switch circuitry may route packets between the first real time network and the one or more second real time networks based on a mapping. Routing information may be inserted in packets routed from the one or more second real time networks to the first real time network and routing information may be removed from the packets routed from the first real time network to the one or more second real time networks. Packets may be routed based on the mapping to distinct queues for the first and second traffic.
US10164788B2
The present disclosure relates to a method and a system for remote control, and a remote control method using a control user interface of a remote user interface (UI) client according to an exemplary embodiment of the present invention includes receiving, by the remote UI client, a message requesting a service from a remote device; transmitting a message requesting a control UI related to the requested service to a remote UI server when the remote UI client receives the message requesting the service from the remote device; receiving, by the remote UI client, a control UI corresponding to the message requesting the control UI from the remote UI server; and transmitting, by the remote UI client, the received control UI to the remote device. According to an exemplary embodiment of the present invention, a user may easily control a corresponding remote user interface through a control user interface specified for a screen on which the remote user interface is being reproduced.
US10164781B2
Interworking between a policy decision device and an address translation device is provided. An operation method of the policy decision device in a mobile communication system includes, if receiving address translation information about a user equipment, determining translated address information about the user equipment using the address translation information, if receiving a service information request for the user equipment, distinguishing the user equipment using address information included in the service information request and the translated address information, and sending a response to the service information request.
US10164773B2
Described is an apparatus comprising precharge paths including first clocked transistors having gates coupled to a clock signal path, first terminals coupled to a first power rail, and second terminals coupled to one or more first junction nodes. The precharge paths lack a keeper circuitry, have a configurable keeper circuitry, and/or have cross-coupled keeper circuitry to eliminate/reduce keeper contention during domino logic evaluation. The apparatus may comprise second clocked transistors having gates coupled to the clock signal path, first terminals coupled to one or more second junction nodes, and second terminals coupled to a second power rail. The apparatus may comprise sets of evaluation transistors having conducting channels coupled in series, coupled to the one or more first junction nodes, and coupled to one of the one or more second junction nodes. A NAND or inverter circuitry with inputs is coupled to the one or more first junction nodes.
US10164762B2
The present invention is directed towards a method, a system, and a device which allow an improved synchronization of a system-wide timing information over a network. Hence, slave clocks can be synchronized to a high quality clock, such as a master clock.
US10164760B1
Systems and methods are disclosed for detecting and compensating for timing excursions in a data channel. If a signal contains discontinuities in phase, a detector of the channel may lose lock on the signal, resulting in the channel incorrectly adjusting a sampling phase toward a following symbol or previous symbol. This is referred to as a cycle slip, where the integer alignment of the sampling of a signal contains a discontinuity over the duration of a sector, preventing decoding of the signal. A circuit may be configured to detect a cycle slip during processing of a signal at a data channel based on timing error values, and when the signal fails to decode, shift an expected sampling phase of a detector for a subsequent signal processing attempt. Shifting the expected sampling phase can cause the channel to adjust the sampling phase in the correct direction, thereby preventing a cycle slip.
US10164753B2
A wireless communication apparatus is capable of improving communication efficiency by reducing the amount of control information transmitted. A channel quality information extraction section extracts CQI's from a received signal. An allocation control section allocates subcarriers for every communication terminal apparatus and selects a modulation scheme in such a manner that required transmission rate is satisfied for each communication terminal apparatus based on required transmission rate information, etc. and CQI's for communication terminal apparatus of each user. A required subcarrier number determining section decides the number of subcarriers allocated to every communication terminal apparatus so as to satisfy the required transmission rate for each communication terminal apparatus. A required subcarrier number information generating section generates information for the number of subcarriers allocated to every communication terminal apparatus. A subcarrier allocation section allocates packet data to selected subcarriers. Modulating sections adaptively modulate packet data allocated to each subcarrier.
US10164751B2
Methods and nodes are provided for transmission of information, over at least one antenna port, in a subframe, which information is received by a receiver in a wireless communication system. Demodulation of the information entity by the receiver is enabled by also transmitting a Demodulation Reference Signal, DM-RS, comprising a DM-RS pattern, wherein positions in the DM-RS pattern are associated with at least one antenna port for transmission of the information entity. The method includes defining, for at least one subframe, a set of at least two distinct DM-RS patterns, assigning one DM-RS pattern, from the defined set of DM-RS patterns, to the receiver, and transmitting the information entity on the at least one antenna port associated with the assigned DM-RS pattern.
US10164740B2
An apparatus and method for multiplexing signals using layered division multiplexing are disclosed. A signal multiplexing apparatus according to an embodiment of the present invention includes a combiner configured to combine a core layer signal and an enhanced layer signal at different power levels to generate a multiplexed signal, a power normalizer configured to reduce power of the multiplexed signal to power corresponding to the core layer signal, and a time interleaver configured to perform interleaving applied to both the core layer signal and the enhanced layer signal.
US10164735B2
Embodiments relate to the communications field, and provide an adaptive modulation and coding method, apparatus, and system. The method includes: obtaining to-be-processed data; obtaining channel information corresponding to the to-be-processed data, and determining a modulation mode according to the channel information. The method also includes determining first data and second data from the to-be-processed data according to the modulation mode; performing soft decision forward error correction FEC coding on the first data to obtain a first bit stream. The method also includes obtaining a second bit stream according to the second data, and modulating the first bit stream and the second bit stream according to a constellation mapping rule; and sending modulated data.
US10164732B2
An encoding circuit for selecting a transmit data symbol for transmission over a data bus may include an alternate symbol generation circuit configured to generate an alternate data symbol based on an encoded data symbol scheduled for transmission over the data bus and a decision circuit configured to select the encoded data symbol or the alternate data symbol as the transmit symbol based on a plurality of phasors. The decision circuit may include a plurality of phasor generation circuits configured to generate the plurality of phasors based on the encoded data symbol and a plurality of target frequencies.
US10164729B2
A system including a direct current tone, guard tone, data tone allocation, mapping, and inverse Fourier transform (IFT) modules. The direct current tone module determines a number of direct current tones based on whether a network device is operating in a single user or multi-user mode. The guard tone module determines a number of guard tones based on whether the network device is operating in the single user or multi-user mode. The data tone allocation module determines a number of data tones based on the number of direct current and guard tones. The mapping module receives data and based on the number of data tones, maps the data to the data tones. The IFT module performs a frequency to time domain conversion of an output of the mapping module to generate orthogonal frequency division multiplexing (OFDM) symbols during the single user mode and OFDM access symbols during the multi-user mode.
US10164725B2
A method of measuring a time difference between detection times includes receiving, from a first sensor, first information associated with a first detection time at which a first biosignal is detected, receiving, from a second sensor, second information associated with a second detection time at which a second biosignal is detected, and measuring a time difference between the first and the second detection times based on the first information and the second information.
US10164718B2
A transmission apparatus (10) includes a communication device (30), comprising two input/output terminals (20a, 20b), and a terminal line (40) connected to the first input/output terminal (20a) and having an electrical length of substantially 90°. By the second input/output terminal (20b) electrically coupling with a transmission medium (50) comprising a conductor or a dielectric, a high frequency signal or electric power is transmitted to another transmission apparatus coupled electrically to the transmission medium (50).
US10164713B2
An optical transmitter includes: a driving circuit that includes drivers each corresponding to a configuration bit of an input electrical data sequence; a MZ optical modulator that includes a first phase shifter provided in an arm and a second phase shifter provided in an arm; first capacitance elements that are electrically connected between the driving unit and the first phase shifter, each include an electric capacity weighted in response to a bit number of the configuration bit, and generate a first multilevel signal to be supplied to the first phase shifter; and second capacitance elements that are electrically connected between the driving circuit and the second phase shifter, each include an electric capacity weighted in response to a bit number of the configuration bit, and generate a second multilevel signal to be supplied to the second phase shifter.
US10164704B2
A satellite transmitter module for accepting input signals and emitting output signals for uplink transmission. The module includes a transmitter unit that includes i) transmitter circuitry, ii) at least one input port, iii) and at least one output port. At least one heat sink coupled to the transmitter unit includes a plurality of heat sink fins, wherein at least two of the plurality of heat sink fins are of different heights. A fan is capable of generating air flow parallel with the plurality of heat sink fins. The module further includes an outer enclosure that i) encloses the transmitter unit and the plurality of heat sink fins and ii) is impermeable to the air flow generated by the fan. The outer enclosure includes an enclosure cross section shape that is substantially similar to the at least one heat sink cross section shape defined by the height of each of the plurality of the heat sink fins.
US10164694B2
There is provided mechanisms for beamforming using an antenna array. A method is performed by a network node. The method comprises obtaining, from a wireless device, a precoding matrix indicator to be used for transmission to the wireless device. The method comprises selecting a codebook from a set of codebooks according to the received indicator, wherein the selected codebook defines the precoding matrix, and wherein the set of codebooks comprises codebooks defining variable beam widths and having same number of non-zero antenna weights for all beam widths. The method comprises precoding transmission of signals to the wireless device from the antenna array using the selected codebook.
US10164690B2
The disclosure discloses a method and device for forming a multi-cell beam. The method includes: a beam forming vector bq of each coordination cell in a heterogeneous network is calculated according to a principle of maximizing a signal intensity of a coordination cell scheduling user and minimizing a weighted interference leakage of the coordination cell scheduling user to other coordination cell scheduling users; and the beam forming vector bq of corresponding coordination cell is updated according to a calculation result, to enable each coordination cell to transmit data to a corresponding scheduling user according to updated beam forming vector bq.
US10164689B2
Embodiments described herein relate to a host unit for a distributed antenna system. The host unit includes a first radio access network (RAN) interface module to communicate with a RAN node. The host unit also includes a distribution module configured to distribute transport signals between one or more downstream RJ45 connectors and the first RAN interface module. One or more non-permanent connectors are included to couple the distribution module to a second RAN interface module and one or more upstream RJ45 jacks. The one or more upstream RJ45 jacks are configured to pass Ethernet signals therethrough. The distribution module is configured to couple a downlink portion of the first transport signals and either a downlink portion of the second transport signals or a downlink Ethernet signal from one of the upstream RJ45 jacks to a first twisted pair cable connected to one of one or more downstream RJ45 jacks.
US10164680B2
A radio communication device is provided with a VOX function. A reception completion state determination unit determines whether or not a reception unit is in a state of completing reception. A timer starts to measure a predetermined time when the reception completion state determination unit determines that the reception unit is in the state of completing the reception. A VOX level selection unit sets a VOX level at which the VOX function determines that transmission is made to a first VOX level after the timer finishes measuring the predetermined time, and sets the VOX level to a second VOX level smaller than the first VOX level while the timer is measuring the predetermined time.
US10164679B1
An electronic device may have conductive housing structures and first, second, third, and fourth slot antennas having respective first, second, third, and fourth slot elements in the conductive housing structures. The third slot element may be interposed between the first and second slot elements and the second slot element may be interposed between the third and fourth slot elements. Switching circuitry may be coupled between a transceiver and the slot elements. Control circuitry may control the switching circuitry to activate a selected pair of the slot antennas based on an orientation of the device or other data. The active pair of antennas may convey radio-frequency signals at the same frequencies using a multiple-input and multiple-output (MIMO) communications scheme. In this way, the device may perform wireless communications at relatively high data throughputs regardless of how the device is being held by a user.
US10164677B2
The present disclosure relates to devices and methods for initiating execution of actions and for communicating information to a user, and more particularly, to initiating execution of predefined actions in wearable devices and communication devices based on gestures made with the wearable devices and/or heat applied to a surface of the wearable devices. According to an aspect, the method relates to, in the wearable device, detecting a first, in the first wearable device predefined, gesture of the first wearable device, broadcasting a first signal comprising information associated with the first gesture, receiving, from a second wearable device, a second signal comprising information associated with a second gesture and initiating execution of a, in the first wearable device predefined, first action based on the first signal and the second signal.
US10164671B2
An echo cancellation circuit is provided to reduce or eliminate the effects of a pre-echo signal that is part of a received multi-path signal. The circuit includes: a delay module, receiving an input signal and delaying the input signal to generate a plurality of delayed signals; a multiplication module, multiplying the plurality of delayed signals by a plurality of coefficients to generate a plurality of multiplication results, respectively; a summing circuit, performing a summation on the plurality of multiplication results to generate a summation signal; a subtraction circuit, receiving a first delay signal and generating a subtracted signal according to the first delayed signal and the summation signal; and a coefficient calculating circuit, calculating the plurality of coefficients according to the subtracted signal. The echo cancellation circuit outputs an output signal as the subtracted signal, with the pre-echo signal diminished or eliminated.
US10164667B1
Spatial power-combining devices having amplifier connectors are disclosed. A spatial power-combining device structure includes a plate including a first face, a second face that opposes the first face, an exterior surface between the first face and the second face, and a plurality of amplifier connectors accessible at the exterior surface. A waveguide assembly is coupled to the plate at the first face, the waveguide assembly including an inner housing including a plurality of antenna signal conductors and an outer housing including a plurality of antenna ground conductors. A coaxial waveguide section is coupled to the waveguide assembly. The plurality of amplifier connectors may be radially arranged in the plate. A plurality of amplifier modules are on the exterior surface and coupled to corresponding ones of the plurality of amplifier connectors.
US10164660B1
An integrated circuit may include a Reed-Solomon decoder that receives a transmitted code word and an associated bit mask and that generates a corresponding corrected message. The bit mask indicates an erasure pattern for the received code word. The Reed-Solomon decoder may include a syndrome generator, a multiplication circuit, a read-only memory (ROM) circuit, an address compressor, and an aggregation circuit. The syndrome generator may receive the transmitted code word and generate a corresponding syndrome. The address compressor may receive the bit mask and generate a corresponding unique address for accessing the ROM circuit. The ROM circuit may then output an inverse parity matrix based on the unique address. The multiplication circuit may multiply the syndrome by the retrieved inverse parity matrix to output corrected symbols. The aggregation circuit may then path the received code word with the corrected symbols to obtain the corrected message.
US10164655B2
Techniques for generating parities and repairing data erasures using a cache oblivious encoding algorithm are disclosed. The system includes an encoding module which receives a request to recreate data for a subset of a plurality of content stores from a storage manager. The encoding module generates a new first parity and a new second parity using the remaining content in the plurality of content stores. The encoding module generates a first portion of the requested data using the new first parity and a first parity for the plurality of content stores and a second portion of the requested data using the new second parity and a second parity for the plurality of content stores. The encoding module may recreate the data for the plurality of content stores using the first portion of the requested data and the second portion of the requested data.
US10164648B2
A device includes a lock detect circuit that is structured and arranged to: convert a reference clock to a reference triangle wave; convert a feedback clock to a feedback triangle wave; determine whether the feedback triangle wave is within a tolerance margin that is defined relative to the reference triangle wave; and generate a determiner output that is a first value when the feedback triangle wave is not within the tolerance margin, and a second value when the feedback triangle wave is within the tolerance margin.
US10164644B2
Methods, devices and computer-readable mediums for clock synchronization are provided. The methods include receiving a synchronizing clock in a unit clock cycle of a measuring clock, calibrating position information of a rising edge of the synchronizing clock in the unit clock cycle, determining a phase difference between the measuring clock and the synchronizing clock in the unit clock cycle based on the calibrated position information, and compensating a photon time in the unit clock cycle with the determined phase difference as a time compensation value.
US10164641B2
Embodiments of the present invention relate generally to logic devices, and more particularly, to magnetoelectric magnetic tunneling junction computational devices. Aspects of the disclosed technology include a stand-alone voltage-controlled magnetoelectric device that satisfies essential requirements for general logic applications, including nonlinearity, gain, concatenability, feedback prevention, and a complete set of Boolean operations based on the majority gate and inverter. Aspects of the present disclosed technology can eliminate the need for any auxiliary FETs to preset or complicated clocking schemes and prevents the racing condition.
US10164640B1
Disclosed is a physical unclonable function generator circuit and method. In one embodiment, a physical unclonable function (PUF) generator includes: a PUF cell array comprising a plurality of bit cells, wherein each of the plurality of bit cells comprises at least two inverters, at least one floating capacitor, at least two dynamic nodes, wherein the at least one floating capacitor is coupled between a first inverter at a first dynamic node and a second inverter at a second dynamic node; a PUF controller coupled to the PUF cell array, wherein the PUF controller is configured to charge the first dynamic nodes through the respective first inverters in the plurality of bit cells; and a finite state machine coupled to the PUF cell array configured to determine voltage levels on the second dynamic nodes through the respective second inverters in the plurality of bit cells to determine first logical states of the plurality of bit cells at at least one sampling time and generate a PUF signature.
US10164637B2
A device and method for shifting voltage levels within a circuit are provided. An aspect of the disclosure provides a level shifting circuit for shifting a first logic domain to a second logic domain. In particular, the level shifting circuit can receive an input signal having a first logic domain with a first high voltage and a first low voltage. The level shifting circuit can receive inputs corresponding to a second high voltage and a second low voltage from the second logic domain. The level shifting circuit can concurrently switch the first high voltage and first low voltage at the input to the second high voltage and the second low voltage to produce a level-shifted version of the input signal at the output. The level shifting circuit can also have a plurality of guard transistors that prevent overvoltage of the circuit components.
US10164634B2
An impedance calibration circuit includes a first detection unit configured to generate a first pull-up impedance detection signal according to a resistance value of an internal reference resistor, a second detection unit configured to generate a second pull-up impedance detection signal according to a resistance value of an external reference resistor coupled to an external reference resistor pad, a switching unit configured to select the first pull-up impedance detection signal or the second pull-up impedance detection signal according to the internal impedance calibration enable signal and output the selected pull-up impedance detection signal, and an impedance calibration signal generation unit configured to generate a plurality of impedance calibration signals according to an output of the switching unit.
US10164630B2
An activation device for actuation of a vehicle function includes a cover element, a light distribution device arranged under the cover element, and a light source arranged under or in the light distribution device. The light source and the light distribution device are arranged for backlighting the cover element. The cover element includes an outward directed operation area at least partially formed of an electrically-conductive metallic material with the operation area being galvanically decoupled from the remaining components. A circuit board is arranged under the light distribution device with a capacitive sensor such that the capacitive sensor is coupled to the operation area. The control and evaluation circuit is coupled to the light source and the proximity sensor to control the light source depending on an approach.
US10164629B2
In one aspect of the teachings herein, a switching circuit for switching a power transistor is configured to control the slew rate of the switched load current in a manner that yields substantial independence from the load voltage, based on the use of a Miller-effect compensation capacitor and controllable source resistances for driving the gate or base of the power transistor. In a non-limiting example, a control circuit, such as a microcontroller, uses a set of bidirectional input/output ports to drive the transistor base or gate through a selectable combination of parallel resistors, so that the effective source resistance for transistor turn-on and turn-off is selectable by configuring different combinations of input/output settings for the set of bidirectional input/output ports. Controlling the source resistance in this manner allows the control circuit to set or otherwise control the slew rate of the load current.
US10164628B2
A switch box includes a relay transistor circuit connecting a pair of batteries in parallel, and an breaker circuit that breaks the relay transistor circuit when a sign of a potential difference between a potential of at least one of the pair of batteries connected to the relay transistor circuit and a predetermined reference potential is reversed with respect to the sign of the potential difference in which the batteries are correctly connected.
US10164624B2
Apparatuses for reducing leakage currents during an off state for transistors is described herein. An example apparatus includes a switch having an input node and an output node. The switch is configured to couple a signal on the input to the output node when the switch is in an on state and is further configured to decouple the input and output nodes when the switch is in an off state. The switch includes first and second transistors, and further includes third and fourth transistors. A drain electrode of the first transistor is coupled to a source electrode of the third transistor, a drain electrode of the second transistor is coupled to a source electrode of the fourth transistor, and the drain electrodes of the third and fourth transistors are coupled together to the output node.
US10164620B1
A ringing suppression circuit, which is connected to a transmission line for transmitting a differential signal changeable between a high level and a low level in a binary level through a pair of a high potential side signal line and a low potential side signal line, and suppresses ringing that occurs in association with transmission of the differential signal, includes: an inter-line switching element that is connected to the pair of the high potential side signal line and the low potential side signal line; and a control unit that turns on the inter-line switching element and fixes an on state when detecting that the differential signal changes from the high level to the low level, and releases the on state after a predetermined time is measured and elapsed.
US10164619B2
A method of controlling a clock frequency of an electronic device and an electronic device using the same is provided. The electronic device includes a check module that is configured to check a clock frequency of at least one Radio Frequency (RF) band, and a control module that is configured to shift a clock frequency of a high speed signal such that a noise generation clock frequency and the clock frequency of the at least one RF band checked by the check module are not identical, when an interface of the high speed signal is used.
US10164610B2
A signal output device is provided in a communication apparatus. The communication apparatus communicates with a different one of the communication apparatus using a single line. The signal output device includes a signal output unit. The signal output unit includes a first filter and a second filter. The first filter is provided by a Bessel filter. The second filter is provided by a Chebyshev filter or a Butterworth filter. The signal output unit outputs a signal which is obtained by passing a predetermined signal through the first filter and the second filter. The signal output from the signal output unit has a pass characteristic of the first filter and a pass characteristic of the second filter. A cutoff frequency of the first filter is set to be lower than a cutoff frequency of the second filter.
US10164608B2
Switch comprising at least one PCM portion that can be in a conducting or blocked state depending on the amorphous or crystalline state of the PCM that can change state when it is heated, in which the PCM portion is continuous and has an elongated shape such that an input and an output of the switch are connected to two ends of the PCM portion respectively that are separated from each other by a distance corresponding to the largest dimension of the PCM portion, and comprising a control device of the state of the switch capable of passing heating currents through the PCM portion, approximately perpendicular to the largest dimension of the PCM portion, from at least two input points separated from each other and separated from the ends of the PCM portion, to at least two output points separated from each other and separated from the ends of the PCM portion.
US10164606B1
A load-compensated tunable coupler leverages a cross-bar switch and simulated loads or ballasts to provide a tunable coupling between two quantum objects that can be selectively coupled or decoupled without changing their resonant frequencies.
US10164594B2
A circuit is formed on an SOI. The bias generator is connected to the gates of first and second transistors. In the bias generator, a first variable current source is connected to the power supply circuit via a power supply node. A third transistor is connected between the first variable current source and a ground-voltage source. A gate thereof is connected to the gate of the first transistor. A first operational amplifier controls a gate voltage of the third transistor so that a voltage at a second node between the first variable current source and the third transistor becomes almost equal to a reference-voltage. A first characteristics changer is connected to the gate of the third transistor or a second node, to change at least one loop gain characteristics and phase characteristics of a loop from the first operational amplifier, through the third transistor, to the first variable current source.
US10164591B1
Certain aspects of the present disclosure provide methods and apparatus for amplifying signals with an amplification circuit and improving a common-mode rejection ratio (CMRR) thereof. The amplification circuit generally includes a differential amplifier comprising a first pair of transistors and a second pair of transistors coupled to the first pair of transistors, where the gates of the first pair of transistors are coupled to respective differential input nodes. The amplification circuit also includes an auxiliary amplifier comprising a third pair of transistors corresponding to the first pair of transistors and a fourth pair of transistors corresponding to the second pair of transistors, where drains of the third and fourth pairs of transistors are coupled together and to gates of the second pair of transistors and where gates of the fourth pair of transistors are coupled together.
US10164586B2
An impedance-matching circuit includes a resonant circuit, first and second capacitors, and first through third inductive circuits. The resonant circuit includes a fourth inductive circuit connected in parallel with a capacitive circuit. The impedance-matching circuit receives a radio frequency power amplifier (RFPA) output signal, which includes first and second signals at first and second frequencies, respectively. A resonant frequency of the resonant circuit is between the first and second frequencies. The resonant circuit offers inductive and capacitive impedances to the first and second signals, respectively. The impedance-matching circuit generates a matched RFPA output signal including the first signal and the second signal, where the second signal is at a reduced voltage level.
US10164580B2
A gate bias circuit for a plurality of GaAs amplifier stages is a transistor coupled to a temperature compensation current received from a CMOS control stage. A plurality of pHEMPT amplifier stages are coupled to the gate bias circuit and to a control voltage which switches the amplifier stage. A selectively controlled stage pass transistor enables a current mirror between the gate bias circuit and each stage amplifying transistor. The penultimate pHEMPT amplifier stage is coupled to a CMOS amplifier. A CMOS circuit provides both the temperature compensation current by a proportional to absolute temperature (PTAT) circuit and the control voltage enabling each pHEMPT transistor to receive its input signal in combination with the gate bias voltage.
US10164569B2
A signal generator and an associated resonator circuit are provided. The signal generator includes the resonator circuit and a core circuit. The resonator circuit further includes a first inductor (L1), a second inductor (L2), a plurality of capacitors and a switching circuit. The first inductor (L1) has a first terminal (N1) and a third terminal (N3), and the second inductor (L2) has a second terminal (N2) and a fourth terminal (N4). The switching circuit includes a first switch (S1), a second switch (S2), a third switch (S3) and a fourth switch (S4). The core circuit further includes a first inner circuit, a first outer circuit, a second inner circuit, and a second outer circuit. Configurations of these switches are adjustable and resonance caused between these terminals is changed accordingly.
US10164567B2
In one embodiment, harmful solar cell polarization is prevented or minimized by providing a conductive path that bleeds charge from a front side of a solar cell to the bulk of a wafer. The conductive path may include patterned holes in a dielectric passivation layer, a conductive anti-reflective coating, or layers of conductive material formed on the top or bottom surface of an anti-reflective coating, for example. Harmful solar cell polarization may also be prevented by biasing a region of a solar cell module on the front side of the solar cell.
US10164566B2
A system and method for a photovoltaic (PV) module is disclosed that includes a microinverter assembly having a housing disposed on an inactive surface of a PV panel and a microinverter disposed within the housing. The PV module also includes a mounting bracket having a central bracket portion coupled to a frame of the PV panel, a first extension portion extending from the central bracket portion and coupled to the housing, a second extension portion extending from the central bracket portion and positioned on the inactive side of the PV panel, and a third extension portion located above the second extension portion and extending from the central bracket portion. At least one of the second and third extension portions is in contact with an inner wall of the frame of the PV panel.
US10164558B2
An electric motor control device includes a control unit that controls operation of a drive circuit supplying electric power to an electric motor and a current sensor that detects current generated in the electric motor. The control unit detects fundamental high frequency current generated when the electric motor is applied with fundamental high frequency voltage for estimating the magnetic pole position, selects first electric angle and second electric angle corresponding to a d-axis direction of the magnetic pole position, detects first specific high frequency current generated when a position of the first electric angle is applied with specific high frequency voltage and second specific high frequency current generated when a position of the second electric angle is applied with the specific high frequency voltage, and compares the first and the second specific high frequency currents to estimate a positive d-axis direction of the magnetic pole position.
US10164552B2
A disclosed power generating device includes: a first magnetostrictive bar; a second magnetostrictive bar extending alongside the first magnetostrictive bar; a joint member coupling the first magnetostrictive bar and the second magnetostrictive bars; and a coil group including a first coil wound around the first magnetostrictive bar and a second coil wound around the second magnetostrictive bar, wherein the first coil and the second coil are connected in series.
US10164549B2
Disclosed is a power module cascaded converter system, a control sub-system thereof includes a master controller, and is provided with switch modules corresponding one-to-one to power modules. For each switch module, before the corresponding power module is removed, a driver circuit thereof can drive the switch circuit into a closed state through a control signal sent from the master controller, so as to bypass the power module. An optical-electric module in the power module cascaded converter system converts an optical signal input from an optical fiber into an electrical signal. With a first control port of each switch module, which is detachably and electrically coupled to a second control port of the power module, the power module cascaded converter system can support insertion and extraction of the power module without cutting off electricity, thereby adding flexibility and convenience for replacing power modules.
US10164545B2
A power distribution system in which a power source is configured to supply an amount of high-frequency input power to a centralized frequency converter unit. The centralized frequency converter unit is configured to convert the high-frequency input power into low-frequency converted power. Passenger Electronic Device Controllers receive the converted power and distribute it to outlet units. Power management functions may be integrated with the distribution system. For instance, the centralized frequency converter unit can cause to be disabled unused outlet units when the power drawn by the used outlet units exceeds a predetermined threshold.
US10164542B2
A converter includes first and second input terminals and first and second output terminals. The converter also includes an output capacitor coupled between the first output terminal and the second output terminal, and a magnetic component having two input terminals and three output terminals. A first output terminal of the magnetic component is coupled through a first electronic switch to the second output terminal of the converter, a second output terminal of the magnetic component is coupled to the first output terminal of the converter, and a third output terminal of the magnetic component is coupled through a second electronic switch to the second output terminal of the electronic converter. In addition, the converter includes a switching stage configured to transfer current pulses from the first input terminal and the second input terminal of the converter to the two input terminals of the magnetic component.
US10164541B2
A power supply unit includes a conversion circuit that performs power conversion of power input into the power supply unit to supply direct-current power to an output path of the power supply unit, a control circuit that controls the conversion circuit so that output voltage supplied from the conversion circuit to the output path has a fixed value if output current supplied from the conversion circuit to the output path is lower than or equal to an overcurrent trip point and controls the conversion circuit so that the output voltage is decreased if the output current exceeds the overcurrent trip point, a monitoring circuit that monitors a discharge output from a discharge circuit to the output path, and a trip point changing circuit that increases the overcurrent trip point if the discharge output monitored by the monitoring circuit is decreased to a threshold value.
US10164534B2
A converter can include: (i) a first switch having a first terminal for receiving an input voltage, and a second terminal coupled to a first terminal of a second switch; (ii) an inductor having a first terminal coupled to a common node of the first and second switches, and a second terminal coupled to a first terminal of a third switch, where second terminals of the second and third switches are coupled to ground; and (iii) a plurality of output channels coupled to a common node of the inductor and the third switch, where the converter operates in a buck-boost mode, a buck mode, or a boost mode based on the relationship between the input voltage and output voltages of the plurality of output channels.
US10164523B2
In a boost chopper circuit, a withstand voltage of at least one device of a switching device circuit is lower than a withstand voltage of a capacitor circuit connected in series to a backflow prevention diode circuit between opposite ends of the switching device circuit.
US10164522B2
A control system for a mild hybrid vehicle is configured to detect whether a main contactor is open, the main contactor being connected between a primary battery system and a bi-directional direct current to direct current (DC-DC) converter and in response to detecting that the main contactor is open: command the DC-DC converter to operate in a boost mode to excite a motor-generator unit (MGU), after the excitation of the MGU has completed, command the DC-DC converter to operate in a buck mode, determine a previous voltage regulation feedback setpoint for the DC-DC converter, and control the DC-DC converter to maintain a voltage of the secondary battery system within a desired range by inserting a delay to a voltage control loop of the DC-DC converter such that the voltage control loop mimics a bandwidth of the MGU.
US10164520B2
A circuit (100) for protecting a Switching Power Converter (“SPC”) when a short-circuit load condition occurs. The SPC has an output current sensor utilizing at least one current transformer that has a primary winding connected in series with a rectifier and has a magnetic core that should avoid saturation. A pulse-width modulator includes a skip controller providing a series of control pulses to at least one switch. A control pulse is skipped when an abnormally low load resistance causes an input current ramp signal to exceed an input current setpoint signal proximate a start time of a next control pulse of the series and the output current is greater than a predetermined threshold. Operation of the SPC is stopped if more than a predetermined number of consecutive switching cycles are skipped to prevent operation of the SPC while the core of an output current transformer is saturated.
US10164513B1
Disclosed is a method of acquiring input and output voltage information by employing a pulse width modulation (PWM) controller, which is in collocation with an input power processing unit, a primary inductor, a switch element, a current-sensing resistor, an output rectifier, and an output filter for converting an alternating current input power into an rectified input power and an output power, and the output power supplies an external load. A current-sensing signal is specifically disposed and applied to calculation of the input voltage and output voltage of the rectified input power when the switch element is turned on and off, respectively. Thus, no resistive voltage divider is needed, and power consumption at no load is greatly improved.
US10164511B2
A vibration motor is disclosed. The vibration motor includes a housing, a substrate engaging with the housing, a vibration unit received in the housing, an elastic member suspending the vibration unit, and a coil assembly interacting with the vibration unit. The elastic member includes a second fixing part having a first segment with a first width, a second segment having a second width smaller than the first width for forming a step, and the vibration unit includes a latch corresponding to and engaging with the step for positioning the elastic member.
US10164501B2
A method and apparatus for operating a reluctance motor. The apparatus comprises a stator and a rotor device. The stator comprises a first stator component and a second stator component. The first stator component has at least three poles. The second stator component has at least three corresponding poles. The at least three poles and the at least three corresponding poles form pole pairs. The rotor device is positioned between the first stator component and the second stator component. The rotor device has two rotor poles.
US10164498B2
A fan device includes: a stator core having a plurality of salient poles that protrude outwards in a radial direction; a rotor magnet that is rotatably provided outside the stator core; and a dustproof cover mounted to the stator core and positioned between the stator core and the rotor magnet, wherein the dustproof cover has a cylindrical part having an inner surface being provided with one or more convex part, the convex part being fitted into a slot gap between distal ends of adjacent two of the salient poles.
US10164495B2
A motor-driven fluid machine has three motor wires. The innermost one of the three motor wires in the radial direction of a rotary shaft on a specific section of an outer end portion of a coil end is defined as a first motor wire. The first motor wire has a first extension, which extends from an inner side toward an outer side in the radial direction of the rotary shaft at a position between the specific section and a downstream side in the extending direction of the motor wires, and a second extension, which is continuous from the first extension and extends from the outer side toward the inner side in the radial direction of the rotary shaft to be connected to a corresponding conductive member.
US10164490B2
In a rotary electric machine according to the present invention, an armature winding includes a plurality of distributed winding bodies that are each produced by winding a single conductor wire that is insulated, that is jointless and continuous, and that has a constant cross-sectional area perpendicular to a longitudinal direction, the conductor wires include first through third coil end portions that link first through fourth rectilinear portions and first through fourth rectilinear portions, and are formed such that radial widths w′ of the first through fourth rectilinear portions are wider than radial widths w of the first through third coil end portions.
US10164488B2
A brushless motor includes a stator disposed along an axis and a rotor disposed radially inward from the stator. The rotor includes a core, a plurality of first magnets and a plurality of second magnets configured to have opposite poles relative to the plurality of first magnets. The plurality of first and second magnets may each have a substantially rectangular cross-section and are in contact with a substantially flat surface carried by the core that faces radially outward.
US10164486B2
The present disclosure relates to a mono- or polyphase electric motor including a stator carrying at least three coils and consisting of 12×N straight teeth extending radially, N being an integer greater than or equal to 1, and of an equal peak divergence alpha, measured at their end from the center of the motor, and a rotor exhibiting P pairs of magnetized poles such that P=5+2×R, P being a non-multiple of three, R being an integer greater than or equal to 0, alpha lying between 360°(12×N)/3 and 360°(12×N)/2.
US10164484B2
Techniques are described herein for leveraging these existing components of electronic devices with wireless or internet connectivity to reduce cost, size and complexity of electronic devices while enabling wireless power transfer. The techniques described herein can also be utilized to new low cost dual-function devices that utilize one or more of the same components for both wireless connectively and wireless power transfer.
US10164480B2
An integrated circuit (IC) includes a first circuit layer that includes a first wireless power transfer (WPT) device, a first chip electrically connected to the first circuit layer, and a first tracking circuit disposed in the first chip. The first WPT device may be configured to extract energy from an electromagnetic signal and provide an output voltage. The first tracking circuit may be powered by the output voltage of the first WPT device and may output tracking data in response to an instruction extracted from the electromagnetic signal.
US10164468B2
A protective cover for a portable electronic device includes a protective shell for receiving and at least partially covering the portable electronic device. The protective cover includes a rechargeable power storage device and an electrical coil proximate a back surface of the shell. The protective cover also includes electrical circuitry configured to transfer first electrical power from the rechargeable power storage device to the installed portable electronic device. The electrical circuitry is also configured to transfer second electrical power from the rechargeable power storage device to the electrical coil. The electrical coil is configured to wirelessly transfer at least a portion of the second electrical power to a second portable electronic device. The protective cover may also include a visual indicator for indicating a status of the wireless transfer of the second electrical power to the second portable electronic device.
US10164467B2
A wireless charging system is disclosed. The wireless charging system includes a detector configured to identify device information related to a device to be powered at a location, a location processor coupled with the detector and configured to deliver location-specific information related to the location to the device to be powered based on the detected device information, a power supply in communication with the location processor configured to wirelessly provide power to the device based on the detected device information, such that the location processor is configured to deliver the location specific information to the device via a first channel, and wherein the power supply is configured to wirelessly provide power to the device via a second channel.
US10164457B2
A charging method and apparatus are provided. The charging method includes obtaining power supply energy needed by a storage system during a power failure, detecting a temperature of an environment in which a supercapacitor is located in order to obtain environmental temperature information of the supercapacitor, where the supercapacitor is configured to provide the power supply energy to the storage system, determining a charging voltage of the supercapacitor according to the environmental temperature information and the power supply energy, and charging the supercapacitor according to the determined charging voltage. Therefore, the supercapacitor can be charged according to an actual charging voltage of the supercapacitor such that a life of the supercapacitor is prolonged.
US10164443B2
Disclosed is a method of controlling frequency of a power system by which a frequency of a power system is regulated using high-speed charging and discharging characteristics of a plurality of energy storage systems (ESSs) and a battery state of charge (SOC), the method including: an operation of comparing, by a control unit, first time information and second time information and performing an exit control mode when the first time information (Before_Exit_time) is equal to or less than the second time information (After_Exit_time); an operation of determining, the control unit, an output amount for each ESS for discharging batteries using a battery discharging amount determining function (Exit_control_output( ) function) when a first parameter value (D_time) preset in the exit control mode is a positive value greater than zero and the second time information (After_Exit_time) is equal to or less than a second parameter value (Clear_time); and an operation of discharging, by the control unit, batteries until the frequency is out of a normal range, when an allocated amount of output for each ESS is calculated.
US10164439B2
Systems, apparatus and methods for seamless metal back cover for combined wireless power transfer, cellular, WiFi, and GPS communications are provided. In one aspect, an apparatus for wirelessly coupling with other devices comprises a metallic cover comprising a first metallic portion separated by a first non-conductive portion from a second metallic portion of the metallic portion to define a first slot. The apparatus further comprises a conductor comprising a first end portion electrically coupled to the metallic cover at the first metallic portion and a second end portion crossing the first end portion and electrically coupled to the metallic cover at the second metallic portion. The metallic cover and the conductor form a coupler configured to wirelessly receive power sufficient to charge or power a load of the apparatus from a wireless power transmitter.
US10164436B2
In a power control system including a first controller configured to control supply of power from a photovoltaic module to a plurality of loads and a second controller configured to control charge/discharge of a storage battery, which is one of the plurality of loads, the first controller controls output following power consumption by the plurality of loads, and the second controller increases, during a self-sustaining operation, charging power of the storage battery and detects output fluctuation from the photovoltaic module or from the first controller along with the increase in the charging power, then based on the detected output fluctuation, controls charge of the storage battery, thus, even if connection to the grid is disconnected, supply power may be replenished by the load power used for supply to the predetermined loads, thereby allowing a stable power supply to the other loads.
US10164434B2
Systems and methods for injecting power into or extracting power out of a power network are provided. In a method, Thevenin parameters, in the form of at least a Thevenin voltage and a Thevenin resistance, of an equivalent Thevenin circuit are obtained with respect to each wire of the PCC. A total Thevenin power for all the wires is obtained, based on a specific amount of power at the PCC and the obtained Thevenin parameters. The method calculates an optimal current to be injected into or extracted from the PCC so as to inject or extract a specific amount of power. The calculation is based on the total Thevenin power and the Thevenin parameters. The method controls an injection or extraction of current at the PCC in accordance with the optimal current.
US10164433B2
A method for balancing electrical grid production with electrical grid demand, according to an exemplary aspect of the present disclosure includes, among other things, adjusting operation of an engine of an electrified vehicle during a drive event to either conserve a state of charge of a battery pack in response to a first grid condition of an electrical grid or deplete the state of charge of the battery pack in response to a second grid condition of the electrical grid.
US10164430B2
A subsea power distribution device and system. The subsea power distribution device comprises a watertight housing accommodating at least one transformer, the transformer having a primary winding and a plurality of secondary windings; input terminals, electrically connected to the primary winding and arranged to be connected to a remote power supply; output terminals, electrically connected to the secondary windings and arranged to be connected to subsea power consuming devices. The switches are arranged to break the connections between each secondary winding and a corresponding output terminal, and the switches are arranged within the watertight housing.
US10164422B2
A method and system for protecting low voltage devices driven by a high voltage circuit is disclosed. The method comprises monitoring an output voltage, from a high voltage block, to a low voltage block. The method further comprises comparing the output voltage with a range of voltages allowable for driving the low voltage block. The range of voltages may be pre-defined or dynamically determined. Furthermore, the method comprises operating a first set of switches and a second set of switches. The first set of switches are operated to feed voltage from the high voltage block to input of the low voltage block, and the second set of switches are operated to feed a plurality of reference voltages to the input of the low voltage block.
US10164421B1
The response of a switch supplying electrical power to a load is periodically tested to ensure proper operation and control over the switch. In the event the switch does not respond to commands from a controller during a test cycle to turn off and open a circuit supplying power to the load, a short circuit is created by a test switch. In this event, a fuse is automatically blown preventing uncontrolled power from reaching the load. In one example, the load can take the form of a resistive heating element in an electric heating blanket or electric heating pad.
US10164399B2
A mid-infrared cascading fiber amplifier device having a source configured to generate a first electromagnetic wave output at a first frequency, a fiber coupled to the source and a pump coupled to the fiber and configured to generate a second electromagnetic wave output at a second frequency, wherein the second frequency is higher than the first frequency and causes the fiber to undergo two or more transitions in response to stimulation by the first electromagnetic wave output at the first frequency, wherein the first transition generates the first electromagnetic wave output approximately at the first frequency and the second transition generates the first electromagnetic wave output approximately at the first frequency.
US10164396B2
There may be provided a laser unit including a display configured to display one or both of electric power consumed by the laser unit and electric energy consumed by the laser unit.
US10164395B2
A tool for disconnecting a battery from an electrical connector pad, the tool having a body connected to at least three prongs, including a first outer prong, a second outer prong, and a middle prong. Each prong has a proximal portion connected to a distal portion by a sloped portion. The middle prong may have a side extension, including a side extension proximal portion, a side extension sloped portion, and a side extension distal portion. The tool may be part of kit comprising at least one battery adapted to be disconnected using the tool.
US10164392B1
A towing vehicle/towed vehicle connection system for operably electrically coupling a towing vehicle to a towed vehicle, the system includes a first transceiver disposed on the towing vehicle to provide a wireless electric power signal. A second transceiver is disposed on the towed vehicle and is wirelessly coupled to the first transceiver to receive the wireless electric power signal. The second transceiver is further coupled to the provide energizing electric power to the towed vehicle.
US10164390B2
A connecting terminal free of dark spots for a light strip, comprising a bracket, wherein the bracket is fixedly provided with two pin groups, each pin group comprises at least two pins, the pins in each pin group are in communication with each other, the pin is made of a conducting material; a light using the connecting terminal free of dark spots for light strip comprises a plurality of light strips and said connecting terminal, the light strip are provided with two connecting jacks at both ends thereof, each connecting jack is connected with one of the pins in each corresponding pin group. The connecting terminal employing the above structure is convenient and rapid; thus realizing the connection free of dark spots of the light strip. The installation is also very convenient. Therefore, the structure is simple and useful, with remarkable technical effects.
US10164380B2
A connector system is disclosed that is configured to provide terminals at a 0.5 mm pitch with providing for high data rates of 10 Gbps or more. In an embodiment, a 4X connector can be provided that is about the size of a convention SFP connector while still supporting relatively high data rates. This connector can be stacked to provide additional density.
US10164364B2
A connector may have a housing having a housing part housing a flat cable, and a mounting member mounted to the housing for locking the flat cable. The mounting member may have a mounting part mounted to at least one of the housing and a circuit board, an elastic part extending in a width direction of the flat cable, an extending part extending in the width direction of the flat cable, and an engaging part engaging with an engaged part formed on the flat cable. The mounting part may be connected to an end part in the width direction of the elastic part. An intermediate region of the extending part may be connected to an intermediate region in the width direction of the elastic part. The engaging part may be connected to an end part in the width direction of the extending part. The elastic part may be elastically deformable in a thickness direction of the flat cable.
US10164356B2
A clamp provides electrical communication between a first conductor and a second conductor. The clamp includes a first housing portion having a first surface, a second surface, a first housing bore, and a cavity, the first housing bore extending along a longitudinal axis. The clamp further includes a clamp member at least partially disposed within the cavity of the first housing portion, the clamp member including a first clamp surface adjacent the second surface of the housing in a facing relationship. The clamp further includes a shaft oriented parallel to the longitudinal axis, the shaft coupling the first housing portion and the clamp member. The clamp further includes a second housing portion movably coupled to the first housing portion by the shaft, the second housing portion including a second housing bore and a second clamp surface, the second housing bore aligned with the longitudinal axis, the second clamp surface adjacent the first surface of the first housing portion in a facing relationship.
US10164352B2
The present invention relates to a bushing for contacting a braid of a line within a connector, the bushing is essentially tapering in an insertion direction in which the bushing is adapted to be inserted into the braid in order to be encompassed thereby. Further, the invention relates to a connector comprising a bushing. In order to provide a bushing which allows for being inserted into the braid in a gentle manner and at the same time allows the braid to be evenly contacted with the bushing for establishing a reliable mechanical and/or electrical connection therewith, the present invention provides that the bushing has a radial elasticity allowing a spring tensioned widening and/or compression of the bushing.
US10164343B2
A communication device includes an antenna system. The antenna system at least includes a dual-polarized antenna, a reflector, a PIFA (Planar Inverted F Antenna), and a fork structure. The reflector is configured to reflect the radiation energy from the dual-polarized antenna. The PIFA is separated from the reflector. The fork structure is positioned between the reflector and the PIFA, and is coupled to the reflector or the PIFA.
US10164340B1
An antenna capable of being joined to an antenna feed perpendicular to a ground plane includes a monopole extending perpendicularly from the ground plane. The antenna feed is joined to the monopole. An innermost shell is provided about the monopole. The innermost shell is made from a dielectric material having a dielectric tensor with high permittivity in the direction of the monopole axis. An intermediate shell provided outside the innermost shell. The intermediate shell also has dielectric tensor having high impedance in the direction parallel to the monopole axis. An outermost shell is provided having a perimeter approximately equal to the length of the monopole. The outermost shell also has a dielectric tensor with high impedance in the direction of the monopole axis.
US10164338B2
A device includes a first antenna and a second antenna. The first antenna may be configured to transmit or receive through an aperture provided by the device. The second antenna may include an array of a plurality of antenna elements configured to transmit or receive through the aperture. The plurality of antenna elements may overlap at least a portion of the first antenna.
US10164337B2
An antenna device of a magnetic coupling type includes a magnetic body having a plate-like shape; and a coil, which is wound around the magnetic body.
US10164321B2
A compact wireless communication includes a first radiating element and a second radiating element, which define and function as a dipole antenna, a feeder circuit including a wireless IC chip coupled with the first and second radiating elements, and a feeder substrate that is provided with the wireless IC chip. The first radiating element is provided to the feeder substrate. The second radiating element is provided to a substrate other than the feeder substrate.
US10164319B2
An approach for determining remote terminal antenna alignment in a satellite communications system is provided. A point in time for an expected conjunction of an a remote terminal antenna, a satellite in communication with the remote terminal and the Sun is determined based on predetermined positional data. An interference level imposed by the Sun on communication signals between the antenna and the satellite is measured at a number of respective points in time. A one of the points in time is determined when the interference is at a peak level. Then information regarding alignment of the antenna with respect to the satellite is determined, wherein the determination of the antenna alignment information is based on a comparison between the one point in time of the peak interference level and the expected point in time of the conjunction of the antenna, the satellite and the Sun.
US10164314B2
The present disclosure relates to an antenna module for installing at an opening of a vehicle roof, wherein the antenna module can be arranged at the opening and can be latched there via at least one spring element, wherein the fastening of the antenna module can be secured to the vehicle roof via a locking element which, in its locking position, blocks a resilient backward movement of the spring element out of the latched position.
US10164297B2
A protective layer system for a metallic lithium-containing anode of a lithium cell, for example a lithium-sulfur cell and/or lithium-oxygen cell. To increase the service life and reliability of the cell, the protective layer system includes a lithium ion-conducting layer, in particular an inorganic layer, on the anode side. The anode-side layer has an anode contact side which rests against or which may be placed against the anode. At least one lithium ion-conducting layer, in particular a polymer layer, which contains at least one agent which is reactable with metallic lithium to form an electrically insulating solid is situated on a side of the anode-side layer opposite from the anode contact side. Moreover, the invention relates to an anode which is equipped with such a protective layer system, a lithium cell, and a lithium battery.
US10164295B2
A lead acid battery including: a positive electrode plate including a positive electrode grid and a positive electrode active material; a negative electrode plate including a negative electrode grid and a negative electrode active material; an electrode plate group including the positive electrode plate, the negative electrode plate, and a separator interposed between the positive electrode plate and the negative electrode plate; a battery container including a plurality of cell chambers each accommodating the electrode plate group and an electrolyte; and a lid sealing an opening of the battery container. A ratio P/N of mass P of the positive electrode active material to mass N of the negative electrode active material is 1.25 or more and 1.65 or less. The negative electrode grid contains bismuth in an amount of 1 ppm or more and 300 ppm or less.
US10164287B2
A method for manufacturing an all-solid battery that includes preparing a first green sheet as a green sheet for at least any one of a positive electrode layer and a negative electrode layer and a second green sheet as a green sheet for a solid electrolyte layer, stacking the first green sheet and the second green sheet to form a stacked body, and firing the stacked body with a setter placed in contact with at least one surface of the stacked body. The setter in contact with the at least one surface of the stacked body is 0.11 μmRa or more and 50.13 μmRa or less in surface roughness.
US10164285B2
A sub-assembly for an electrochemical stack, such as a PEM fuel cell stack, has a bipolar plate with sealing material extending from its upper face, around the edge of the bipolar plate, and onto its lower face. The bipolar plate is preferably a combination of an anode plate and a cathode plate defining an internal coolant flow field and bonded together by sealing material which also provides a seal around the coolant flow field. All of the sealing material in the sub-assembly may be one contiguous mass. To make the sub-assembly, anode and cathode plates are loaded into a mold. Liquid sealing material is injected into the mold and fills a gap between the edge of the plates, and portions of the outer faces of the plates, and the mold. In a stack, sub-assemblies are separated by MEAs which at least partially overlap the sealing material on their faces.
US10164276B2
A fuel cell device is improved for operating conditions during a partial load operation. The fuel cell device comprises a cell stack formed by electrically connecting fuel cells for generating power by fuel gas and oxygen-containing gas; a fuel gas supply unit for supplying the fuel gas to the fuel cells; and a power adjustment unit for adjusting the amount of current that is supplied to an external load and a controller for controlling the fuel gas supply unit and the power adjustment unit. The controller adjusts, during the partial load operation of the fuel cell device and when the fuel gas supplied to the cell stack is at low flow rate. The a relationship between a fuel utilization rate of the cell stack and the amount of power generated by the cell stack can be nonlinear.
US10164260B2
Provided is a method for producing a positive electrode for a nonaqueous electrolyte secondary battery having superior electrical conductivity with high productivity. The production method disclosed herein includes the following steps: a first kneading step (S10) for kneading electrically conductive carbon fine particles and a hydrophobic binder that gels when contacted by water, in N-methyl-2-pyrrolidone (NMP); a second kneading step (S20) for adding a positive electrode active material and water to a first kneaded product obtained in the first kneading step followed by additional kneading; and a step (S30) for forming a positive electrode active material layer on the surface of a positive electrode current collector by coating a second kneaded product obtained in the second kneading step on the positive electrode current collector. The first kneaded product contains moisture, and the ratio of the mass of the moisture to the mass of the NMP is 0.002 or less in the first kneaded product, while in the second kneading step (S20), the water is added at a mass ratio of 0.0022 to 0.0115 based on the mass of the NMP.
US10164259B2
This binder for use in a positive electrode for a lithium ion secondary battery contains a copolymer of both vinyl alcohol and an alkali-metal-neutralized ethylenically unsaturated carboxylic acid.
US10164244B2
A negative electrode mixture for a nonaqueous electrolyte secondary cell according to the present invention includes: a negative electrode active material; a conductive assistant; and a binder. The binder contains a copolymer of vinyl alcohol and an alkali metal-neutralized product of ethylene-unsaturated carboxylic acid.
US10164240B2
A composite anode active material includes a silicon-based material, a metal fluoride, and a carbon-based material. The metal fluoride may be a compound represented by the following formula: MFx, where M is at least one selected from magnesium (Mg), aluminum (Al), titanium (Ti), copper (Cu), zinc (Zn), barium (Ba) and bismuth (Bi), and 0
US10164238B2
The present invention relates to a method for manufacturing a battery protection device and a battery protection device manufactured by the method, and more particularly, a method for manufacturing a battery protection device and a battery protection device which reduce a defect rate and also the number of processes, thus enhancing productivity.
US10164232B2
An electrode body comprising a positive electrode mixture layer, a negative electrode mixture layer, and a thermoplastic-resin separator layer interposed therebetween is manufactured. A manufacturing method of the electrode body includes a preprocessing step of preprocessing a portion to be cut in a long-strip shaped integrated structure in which the separator layer as an accumulated layer of resin particles are interposed at least between the positive and negative electrode mixture layers such that the positive electrode mixture layer, the negative electrode mixture layer, and the separator layer are lowered their volume porosities to 10 to 20%, 10 to 20%, and 5% or less, respectively, and a cutting step of cutting the portion of the long-strip shaped integrated structure having been lowered the volume porosity by a cutting blade.
US10164230B2
Separator including microbial cellulose, method of producing the separator, and use of the separator
Provided is a separator including microbial cellulose, a battery comprising the separator, and a method of producing the separator.
US10164228B2
The battery is sealed by a sealing member including a safety valve for exhausting the gas generated in the battery to the outside of the battery when the pressure in the battery is increased. A part of the sealing member is formed of a member having a melting point lower than that of high-temperature gas generated in the abnormal time and having a ratio of an area of an opening of the battery case to an area of a gas exhaust hole is 3.0×10−5 or more and 9.1×10−3 or less.
US10164203B2
A novel light-emitting element is provided. A light-emitting element that emits red light with high color purity and has high emission efficiency is provided. A full-color light-emitting device having low power consumption is provided. In the light-emitting element that exhibits white light emission, the emission wavelength range of red light is a specific range on the longer wavelength side than the conventional emission wavelength range of red light that is usually used, and an optical element having a specific transmittance in the specific wavelength range is used.
US10164201B2
Provided is a light-emitting element with high external quantum efficiency and a low drive voltage. The light-emitting element includes a light-emitting layer which contains a phosphorescent compound and a material exhibiting thermally activated delayed fluorescence between a pair of electrodes, wherein a peak of a fluorescence spectrum and/or a peak of a phosphorescence spectrum of the material exhibiting thermally activated delayed fluorescence overlap(s) with a lowest-energy-side absorption band in an absorption spectrum of the phosphorescent compound, and wherein the phosphorescent compound exhibits phosphorescence in the light-emitting layer by voltage application between the pair of electrodes.
US10164199B2
Organic metal compounds, and organic light-emitting devices employing the same, are provided. The organic metal compound has a chemical structure represented by formula (I): wherein each R1 can be independently hydrogen, C1-12 alkyl group, C5-10 cycloalkyl group, C3-12 heteroaryl group, or C6-12 aryl group; R2 can be independently hydrogen, halogen, C1-12 alkyl group, C5-10 cycloalkyl group, C3-12 heteroaryl group, or C6-12 aryl group.
US10164193B2
An organic light-emitting device comprising an anode (103); a cathode (109); a light-emitting layer (105) between the anode and the cathode; and an electron-transporting layer (107) comprising an electron-transporting material between the cathode and the light-emitting layer, wherein the cathode comprises a layer of a conducting material (109B) and a layer of an alkali metal compound (109A) between the electron-transporting layer and the layer of conducting material and wherein the electron-transporting material is a conjugated polymer comprising arylene repeat units.
US10164192B2
The present invention relates to a solution or ink composition for fabricating high-performance thin-film transistors. The solution or ink comprises an organic semiconductor and a mediating polymer such as polyacrylonitrile, polystyrene, or the like or mixture thereof, in an organic solvent such as chlorobenzene or dichlorobenzene. The percentage ratio by weight of semiconductor: mediating polymer ranges from 5:95 to 95:5, and preferably from 20:80 to 80:20. The solution or ink is used to fabricate via solution coating or printing a semiconductor film, followed by drying and thermal annealing if necessary to provide a channel semiconductor for organic thin-film transistors (OTFTs). The resulting OTFT device with said channel semiconductor has afforded OTFT performance, particularly field-effect mobility and current on/off ratio that are superior to those OTFTs with channel semiconductors fabricated without a mediating polymer.
US10164191B2
The present invention relates to a methoxyaryl surface modifier. In addition the present invention also relates to organic electronic devices comprising such methoxyaryl surface modifier.
US10164190B2
An organic semiconductor compound and a method for manufacturing the same is provided. The method for manufacturing the organic semiconductor compound may include stirring a solated organic semiconductor and a solated organometallic precursor. Herein, the manufacturing the organic semiconductor compound includes: forming a three-dimensional organic semiconductor compound by allowing the solated organic semiconductor to orthogonally penetrate one or more gaps in a lattice structure of a gelated organometallic precursor formed by stirring the solated organometallic precursor.
US10164182B1
The present disclosure relates to an RRAM device. In some embodiments, the RRAM device includes a lower electrode disposed over a conductive lower interconnect layer. An upper electrode is over the lower electrode and a multi-layer data storage structure is between the lower and upper electrodes. The multi-layer data storage structure has first and second sub-layers. The first sub-layer has a first metal from a first group of metals, a first concentration of a second metal from a second group of metals, and oxygen. The second sub-layer has a third metal from the first group of metals, a non-zero second concentration of a fourth metal from a second group of metals, and oxygen. The non-zero second concentration is smaller than the first concentration and causes conductive filaments formed within the second sub-layer to be wider than conductive filaments formed within the first sub-layer.
US10164178B2
In some embodiments, an integrated circuit includes narrow, vertically-extending pillars that fill openings formed in the integrated circuit. In some embodiments, the openings can contain phase change material to form a phase change memory cell. The openings occupied by the pillars can be defined using crossing lines of sacrificial material, e.g., spacers, that are formed on different vertical levels. The lines of material can be formed by deposition processes that allow the formation of very thin lines. Exposed material at the intersection of the lines is selectively removed to form the openings, which have dimensions determined by the widths of the lines. The openings can be filled, for example, with phase change material.
US10164167B2
A method for producing an electric component (19) is specified, wherein in a step A) a body (1) having at least one cavity (7, 8) is provided. In a step B), the cavity (7, 8) is at least partly filled with a liquid insulation material (13) by means of capillary forces. Furthermore, an electric component (19) is specified wherein a cavity (7, 8) is at least partly filled with an insulation material (13). The insulation material (13) is introduced into the cavity (7, 8) by means of capillary forces. Furthermore, an electric component (19) is specified wherein a cavity (7, 8) is at least partly filled with an organic insulation material (13) and wherein the cavity is at least partly covered by a fired external contacting (17, 18).
US10164164B2
This patent incorporates several new hybrid thermoelectric element and thermoelectric device designs that utilize additional electronic materials to enhance the flow of charges in the thermoelectric elements without changing thermoelectric nature of the thermoelectric material used. The thermoelectric device efficiency is thereby increased and cost and size are lowered. Thermoelectric conversion devices using the new design criteria have demonstrated comparative higher performance than current commercially available standard design thermoelectric conversion devices.
US10164156B2
Structures and formation methods of an image sensor structure are provided. The image sensor structure is provided. The image sensor structure includes a substrate, a photodiode component in the substrate, and a grid structure over the substrate. The grid structure includes a bottom dielectric element over the substrate, a reflective element over the bottom dielectric element, and an upper dielectric element over the reflective element. The reflective element has a sidewall which is anti-corrosive in a basic condition and an acidic condition. The image sensor structure also includes a color filter element over the substrate and surrounded by the grid structure. The color filter element is aligned with the photodiode component.
US10164149B1
An LED panel is disclosed. The LED panel includes LED chips and a mount substrate on which the LED chips are mounted by flip bonding. Each of the LED chips includes a sapphire substrate, a plurality of light emitting cells disposed below the sapphire substrate, and an etched portion formed between the plurality of light emitting cells. Each of the LED chips includes a plurality of color cells formed corresponding to the plurality of light emitting cells on the sapphire substrate to change or maintain the color of light from the corresponding light emitting cells and a plurality of light collecting portions formed corresponding to the plurality of light emitting cells and the plurality of color cells on the bottom surface of the substrate and adapted to collect light from the corresponding light emitting cells on the corresponding color cells.
US10164148B2
Provided is a semiconductor layer light-emitting element having tunneling blocking layers interposed between adjacent active regions, wherein the tunneling blocking layers are semiconductor layers, which do not allow the movement of an electron or a hole at an applied voltage sufficient to activate only one active region among all active regions, and independently separate two adjacent active regions in a quantum region range, so that the semiconductor light-emitting element comprises multiple independent active regions in a vertical direction in a single chip and thus can be driven at high voltages.
US10164144B2
Embodiments transfer thin layers of material utilized in electronic devices (e.g., GaN for optoelectronic devices), from a donor to a handle substrate. Certain embodiments employ bond-and-release system(s) where release occurs along a cleave plane formed by implantation of particles into the donor. Some embodiments may rely upon release by converting components from solid to liquid under carefully controlled thermal conditions (e.g., solder-based materials and/or thermal decomposition of Indium-containing materials). Some embodiments utilize laser-induced film release processes using epitaxially grown or implanted regions as an optically absorptive region. A single bond-and-release sequence may involve processing an exposed N-face of GaN material. Multiple bond-and-release sequences (involving processing an exposed Ga-face of GaN material) may be employed in series, for example utilizing a temporary handle substrate as an intermediary. Particular embodiments form template blanks of high quality GaN suitable for manufacturing High Brightness-Light Emitting Diode (HB-LED) devices.
US10164142B2
A flip chip light emitting diode includes a semiconductor layer comprising an epitaxial layer an N-semiconductor layer, a light active layer and a P-semiconductor layer arranged from top to bottom in series. A first electrode mounted on the semiconductor layer. A second electrode mounted on the semiconductor layer. A insulating layer mounted on the semiconductor layer. The N-semiconductor layer protrudes away from the epitaxial layer to form a protruding portion. The light active layer and the P-semiconductor layer mounts on the protruding portion in series. The insulating layer mounts between the first electrode and the protruding portion, the light active layer, the P-semiconductor layer and the second electrode. The flip chip light emitting diode also comprises a supporting portion, the supporting portion is mounted on a top surface of the epitaxial layer by a connecting portion. The connecting portion has same or different materials with the supporting portion.
US10164139B2
A solar cell unit having a semiconductor body formed as a solar cell and having a front side and a back side, a carrier with a top side enclosed by at least four edges, a bottom side, and a first contact surface, formed on the top side and connected to the first terminal contact, and a second contact surface, connected to the second terminal contact and spaced apart from the first contact surface, and a secondary optical element. A back side of the semiconductor body is non-positively connected to a part of the top side of the carrier. The secondary optical element guides light to the front side of the semiconductor body and at least parts of the bottom side of the secondary optical element are non-positively connected to the front side of the semiconductor body and/or to the top side of the carrier by a polymer adhesive layer.
US10164131B2
Multi-layer sputtered metal seed for solar cell conductive contacts and methods of forming solar cell conductive contacts are described. In an example, a solar cell includes a substrate. A semiconductor region is disposed in or above the substrate. A conductive contact is disposed on the semiconductor region and includes a seed material stack in contact with the semiconductor region. The seed material stack includes a first aluminum layer having a first crystallinity and disposed on the semiconductor layer, and a second aluminum layer having a second crystallinity and disposed on and having an interface with the first aluminum layer. The first crystallinity is different from the second crystallinity.
US10164130B2
A solar cell module includes an upper substrate, a lower substrate opposite the upper substrate, a solar cell panel positioned between the upper substrate and the lower substrate, the solar cell panel including a plurality of solar cells which are arranged in a matrix form and are connected to one another through a wiring member to form strings, a passivation layer configured to package the solar cell panel, a frame configured to surround an outer perimeter of the solar cell panel, a connection terminal configured to connect two adjacent strings in the solar cell panel, and a cover member configured to cover the connection terminal.
US10164124B1
An inverse diode die has a high reverse breakdown voltage, a short reverse recovery time Trr, and is rugged in terms of reverse breakdown voltage stability over long term use in hard commutation applications. The die has an unusually lightly doped bottomside P type anode region and also has an N− type drift region above it. Both regions are of bulk wafer material. An N+ type contact region extends down into the drift region. A topside metal electrode is on the contact region. A P type silicon peripheral sidewall region laterally rings around the drift region. A topside passivation layer rings around the topside electrode. A bottomside metal electrode is on the bottom of the die. The die has a deep layer of hydrogen ions that extends through the N− drift region. The die also has a shallow layer of ions. Both ion layers are implanted from the bottomside.
US10164116B2
FETs and methods for forming FETs are disclosed. A structure comprises a substrate, a gate dielectric and a gate electrode. The substrate comprises a fin, and the fin comprises an epitaxial channel region. The epitaxial channel has a major surface portion of an exterior surface. The major surface portion comprising at least one lattice shift, and the at least one lattice shift comprises an inward or outward shift relative to a center of the fin. The gate dielectric is on the major surface portion of the exterior surface. The gate electrode is on the gate dielectric.
US10164107B2
In some embodiments, in a method, a body structure with a gate structure configured thereon is provided. The gate structure comprises a gate side wall traversing the body structure. A spacer is formed over the gate side wall. A first recess is formed in the body structure. The first recess is formed beside the spacer and extending laterally under the spacer. A recess extension is formed under the first recess to extend a vertical depth of the first recess. Stressor material with a lattice constant different from that of the body structure is grown such that the extended first recess is filled.
US10164106B2
A semiconductor device includes a substrate provided with an electronic device, an interlayer dielectric (ILD) layer formed over the electronic device, a wiring pattern formed on the ILD layer and a contact formed in the ILD layer and physically and electrically connecting the wiring pattern to a conductive region of the electronic device. An insulating liner layer is provided on sidewalls of the contact between the contact and the ILD layer. A height of the insulating liner layer measured from a top of the conductive region of the electronic device is less than 90% of a height of the contact measured between the top of the conductive region and a level of an interface between the ILD layer and the wiring pattern.
US10164091B1
A circuit can include a field-effect transistor having a body, a drain, a gate, and a source. In an embodiment, the circuit can further include a bipolar transistor having a base and a collector, wherein the collector of the bipolar transistor is coupled to the body of the field-effect transistor; and the drain of the field-effect transistor is coupled to the base of the bipolar transistor. In another embodiment, the circuit can include a diode having an anode and a cathode, wherein the source of the field-effect transistor is coupled to the anode of the diode, and the gate of the field effect transistor is coupled to the cathode of the diode. In another aspect, an electronic device can include one or more physical structures that correspond to components within the circuits.
US10164089B1
A power MOSFET including a first transistor and a second transistor is provided. The first and the second transistors respectively include following elements. A well region is located in a substrate structure. A trench gate is disposed in the well region. First doped regions are disposed in the well region at two sides of the trench gate. A first metal layer is disposed on a first surface of the substrate structure and electrically connected to the first doped regions. A second doped region is disposed in the substrate structure. A second metal layer is disposed on a second surface of the substrate structure opposite to the first surface and electrically connected to the second doped region. The well regions of the first and the second transistors are separated from each other. The first and the second transistors share the second doped region and the second metal layer.
US10164082B2
A transistor comprises a substrate comprising a Group III/V compound semiconductor material having a cubic crystalline phase structure positioned on a hexagonal crystalline phase layer having a first region and a second region, the cubic crystalline phase structure being positioned between the first region and the second region of the hexagonal crystalline phase layer. A source region and a drain region are both positioned in the Group III/V compound semiconductor material. A channel region is in the Group III/V compound semiconductor material. A gate is over the channel region. An optional backside contact can also be formed. A source contact and electrode are positioned to provide electrical contact to the source region. A drain contact and electrode are positioned to provide electrical contact to the drain region. Methods of forming transistors are also disclosed.
US10164081B2
The invention relates to a method for manufacturing a heterojunction transistor (1), said method comprising the steps of: forming an implanted area (8) by ionically implanting magnesium, calcium, zinc, or fluorine in a first gallium nitride semiconductor layer (4), having a hexagonal crystalline structure, in the [0 0 0 1] orientation of said crystalline structure; forming a second semiconductor layer (6) on the first semiconductor layer so as to form an electron gas layer (5) at the interface between the first and second layers; and forming a control gate (75) over the second conductive layer (6) and vertically in line with the implanted area (8).
US10164075B2
The transistor includes a gate electrode, a gate insulating film over the gate electrode, an oxide semiconductor film over the gate insulating film, a source electrode and a drain electrode electrically connected to the oxide semiconductor film. The oxide semiconductor film includes a first oxide semiconductor film on the gate electrode side and a second oxide semiconductor film over the first oxide semiconductor film. The first oxide semiconductor film includes a first region in which an atomic proportion of In is larger than that of M (M is Ti, Ga, Sn, Y, Zr, La, Ce, Nd, or Hf). The second oxide semiconductor film includes a second region in which an atomic proportion of In is smaller than that of the first oxide semiconductor film. The second region includes a portion thinner than the first region.
US10164058B2
A semiconductor device with a high radiation tolerance is provided. A semiconductor device comprising a semiconductor substrate, a first body region and a second body region provided on a front surface side of the semiconductor substrate, a neck portion provided between the first body region and the second body region, a first source region formed within the first body region and a second source region formed within the second body region, a first gate electrode provided to face the first body region between the first source region and the neck portion, a second gate electrode provided to face the second body region between the second source region and the neck portion, and an insulating film continuously provided between the first gate electrode and the semiconductor substrate, between the second gate electrode and the semiconductor substrate, and on the front surface side of the neck portion, is provided.
US10164055B2
Vertical channel field effect transistors and methods of forming the same include forming one or more vertical channels on a bottom source/drain layer. A seed layer is deposited on horizontal surfaces around the one or more vertical channels. A metal gate is deposited on the seed layer. A top source/drain layer is deposited above the one or more vertical channels and the metal gate.
US10164048B1
A method includes providing a structure that includes a substrate, a gate structure over the substrate, and a source/drain (S/D) feature including silicon germanium (SiGe) adjacent to the gate structure. The method further includes implanting gallium (Ga) into the S/D feature; performing a first annealing process at a first temperature to recrystallize the SiGe; depositing a conductive material including a metal over the S/D feature after the first annealing process; performing a second annealing process at a second temperature to cause reaction between the metal and the S/D feature; and performing a third annealing process at a third temperature to activate dopants including Ga in the S/D feature.
US10164040B2
A method comprises doping a lower portion of a nanowire to form a first drain/source region, wherein the nanowire is formed over a substrate, doping an upper portion of the nanowire to form a second drain/source region, doping a middle portion of the nanowire to form a channel region, wherein the channel region is between the first drain/source region and the second drain/source region, forming a ring-shaped gate structure surrounding a lower portion of the channel region, wherein the ring-shaped gate structure comprises a vertical portion of a first work-function metal layer and depositing a low-resistivity gate metal layer over a horizontal portion of the first work-function metal layer, wherein the low-resistivity gate metal layer is electrically coupled to the vertical portion of the first work-function metal layer through the horizontal portion of the first work-function metal layer.
US10164037B2
A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate having a top surface, a source region, and a drain region. The semiconductor device structure includes a gate structure over the top surface and extending into the semiconductor substrate. The gate structure in the semiconductor substrate is between the source region and the drain region and separates the source region from the drain region. The semiconductor device structure includes an isolation structure in the semiconductor substrate and surrounding the source region, the drain region, and the gate structure in the semiconductor substrate.
US10164017B2
A semiconductor device having an impurity region is provided. The semiconductor device includes a fin active region having protruding regions and a recessed region between the protruding regions. Gate structures overlapping the protruding regions are disposed. An epitaxial layer is disposed in the recessed region to have a height greater than a width. An impurity region is disposed in the fin active region, surrounds side walls and a bottom of the recessed region, has the same conductivity type as a conductivity type of the epitaxial layer, and includes a majority impurity that is different from a majority impurity included in at least a portion of the epitaxial layer.
US10164015B2
Semiconductor structures and devices including strained material layers having impurity-free zones, and methods for fabricating same. Certain regions of the strained material layers are kept free of impurities that can interdiffuse from adjacent portions of the semiconductor. When impurities are present in certain regions of the strained material layers, there is degradation in device performance. By employing semiconductor structures and devices (e.g., field effect transistors or “FETs”) that have the features described, or are fabricated in accordance with the steps described, device operation is enhanced.
US10164010B1
Methods form integrated circuit structures that include a semiconductor layer having at least one fin. At least three gate stacks contact, and are spaced along, the top of the fin. An insulator in trenches in the fin contacts the first and third of the gate stacks, and extends into the fin from the first and third gate stacks. Source and drain regions in the fin are adjacent a second of the gate stacks. The second gate stack is between the first and third gate stacks along the top of the fin. Additionally, a protective liner is in the trench between a top portion of the insulator a bottom portion of the insulator.
US10164009B1
Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a channel to conduct current, the channel including a first channel portion and a second channel portion, a first memory cell structure located between a first gate and the first channel portion, a second memory cell structure located between a second gate and the second channel portion, and a void located between the first and second gates and between the first and second memory cell structures.
US10164006B1
Field-effect transistor structures for a laterally-diffused metal-oxide-semiconductor (LDMOS) device and methods of forming a LDMOS device. First and second fins are formed that extend vertically from a top surface of a substrate. A first isolation region is arranged between the first fin and the second fin. A body region of a first conductivity type is arranged partially in the substrate and partially in the second fin. A drain region of a second conductivity type is arranged partially in the substrate, partially in the first fin, and partially in the second fin. A source region is arranged within the body region in the first fin. A gate structure is arranged to overlap with a portion of the first fin. A second isolation region is arranged within the first fin, and is spaced along the first fin from the first isolation region.
US10164003B2
A method of forming a metal-insulator-metal capacitor is provided. The method includes forming a first metal plate over a semiconductor substrate, forming a first dielectric layer with a first dielectric constant on a surface of the first metal plate, forming a second dielectric layer with a second dielectric constant on a surface of the first dielectric layer, forming a third dielectric layer with a third dielectric constant on a surface of the second dielectric layer, and forming a second metal plate on a surface of the third dielectric layer. The second dielectric constant is different from the first dielectric constant and different from the third dielectric constant.
US10164000B2
A first device that may include a short tolerant structure, and methods for fabricating embodiments of the first device, are provided. A first device may include a substrate and a plurality of OLED circuit elements disposed on the substrate. Each OLED circuit element may include a fuse that is adapted to open an electrical connection in response to an electrical short in the pixel. Each OLED circuit element may comprise a pixel that may include a first electrode, a second electrode, and an organic electroluminescent (EL) material disposed between the first and the second electrodes. Each of the OLED circuit elements may not be electrically connected in series with any other of the OLED circuit elements.
US10163992B2
A mirror display device includes a mirror module and a display module. The mirror module includes a transparent substrate and a plurality of first mirror patterns. The transparent substrate has a first region and a second region adjacent to the first region. The first mirror patterns are disposed on a surface of the transparent substrate in the first region. The display module includes a display part that emits a light and a plurality of second mirror patterns. The display module is combined with the mirror module on the surface of the transparent substrate in the second region.
US10163991B2
A display device includes a substrate comprising a first plastic layer, a second plastic layer on the first plastic layer, and an inorganic layer between the first plastic layer and the second plastic layer, an inorganic embossed layer on the substrate and comprising a plurality of mountain parts, an organic layer on the inorganic embossed layer, an inorganic buffer layer on the organic layer, a thin film transistor on the inorganic buffer layer, and a display element electrically connected to the thin film transistor.
US10163987B2
A manufacturing method of a display device according to an embodiment of the present invention includes: the display device including a protection plate having a light transmitting part facing an input or output device, and a display substrate having a display area, a light emitting film forming the step of forming an island-like light emitting film containing a light emitting material, in an area other than the display area in the display substrate; an alignment step of aligning the protection plate and the display substrate with each other; and an attaching step of attaching the protection plate to the display substrate.
US10163985B2
A subpixel arrangement structure for a display device includes a plurality of unit pixels each having a red subpixel, a green subpixel, and a blue subpixel. The red, green, and blue subpixels form a delta arrangement. Green subpixels are disposed on a plurality of first subpixel arrangement lines, each of which extends along a direction of a first axis. Two red subpixels and two blue subpixels are alternately disposed along the first axis direction on a plurality of second subpixel arrangement lines. Each of the plurality of second subpixel arrangement lines is positioned between every two of the plurality of first subpixel arrangement lines and extends along the first axis direction.
US10163978B2
Memory cell architectures and methods of forming the same are provided. An example memory cell can include a switch element and a memory element formed in series with the switch element. A smallest lateral dimension of the switch element is different than a smallest lateral dimension of the memory element.
US10163974B2
In some embodiments, the present disclosure relates to a method of forming an absorption enhancement structure for an integrated chip image sensor that reduces crystalline defects resulting from the formation of the absorption enhancement structure. The method may be performed by forming a patterned masking layer over a first side of a substrate. A dry etching process is performed on the first side of the substrate according to the patterned masking layer to define a plurality of intermediate protrusions arranged along the first side of the substrate within a periodic pattern. A wet etching process is performed on the plurality of intermediate protrusions to form a plurality of protrusions. One or more absorption enhancement layers are formed over and between the plurality of protrusions. The wet etching process removes a damaged region of the intermediate protrusions that can negatively impact performance of the absorption enhancement structure.
US10163972B2
A method of forming a semiconductor image sensing device includes: providing a semiconductor substrate; forming a radiation sensitive region and a peripheral region in the semiconductor substrate, wherein the peripheral region surrounds the radiation sensitive region and includes a top surface projected from a backside of the semiconductor substrate and a sidewall coplanar with a sidewall of the semiconductor substrate and perpendicular to the top surface; forming a photon blocking spacer in the peripheral region, wherein the photon blocking spacer covers a portion of the sidewall of the peripheral region; and forming an anti reflective coating adjacent to the photon blocking layer.
US10163967B2
An imaging device with low power consumption. The imaging device includes a plurality of pixels arranged in a matrix, a first circuit, a second circuit, a third circuit, and a fourth circuit. The first circuit has a function of converting an analog signal into a digital signal. The second circuit has a function of detecting a difference between image data of a first frame and image data of a second frame. The third circuit has a function of controlling the frequency of a clock signal. The fourth circuit has a function of generating clock signals of a plurality of frequencies.
US10163944B2
A thin film transistor (TFT) substrate and a display device using the same are disclosed. The TFT substrate includes a first TFT including a polycrystalline semiconductor layer, a first gate electrode, a first source electrode, and a first drain electrode deposited on a substrate, a second TFT separated from the first TFT, the second TFT including a second gate electrode, an oxide semiconductor layer, a second source electrode, and a second drain electrode deposited on the first gate electrode, and a plurality of storage capacitors separated from the first and second TFTs, each storage capacitor including a first dummy semiconductor layer, a first gate insulating layer on the first dummy semiconductor layer, a first dummy gate electrode on the first gate insulating layer, and an intermediate insulating layer on the first dummy gate electrode.
US10163932B1
A ferroelectric random-access memory structure and processes for fabricating a ferroelectric random-access memory structure are described that includes using a molybdenum sulfide layer. In an implementation, a ferroelectric random-access memory structure in accordance with an exemplary embodiment includes at least one FeFET, which further includes a substrate; a back gate electrode formed on the substrate, the back gate electrode including a conductive layer; a gate dielectric substrate formed on the back gate electrode; a source electrode formed on the gate dielectric substrate; a drain electrode formed on the gate dielectric substrate; and a layered transition metal dichalcogenide disposed on the gate dielectric substrate and contacting the source electrode and the drain electrode.
US10163929B2
The invention is related to a method for manufacturing a semiconductor device having a barrier pattern. The method includes alternately forming first sacrificial layers and insulating layers forming channel patterns penetrating the first sacrificial layers and the insulating layers, and forming a slit penetrating the first sacrificial layers and the insulating layers. In order to form the barrier pattern, the method also includes forming openings by removing the first sacrificial layers through the slit, and respectively forming conductive layers in the openings. The conductive layers include first barrier patterns having inclined inner surfaces and metal patterns in the first barrier patterns.
US10163926B2
A memory device memory device includes a multi-layers stack, a charge-trapping layer, a first channel layer and a SSL switch. The multi-layers stack includes a plurality of insulating layers, a plurality of conductive layers alternatively stacked with the insulating layers and at least one first through opening passing through the conductive layers. The charge-trapping layer blankets over a sidewall of the first through opening. The first channel layer is disposed in the first through opening. The SSL switch is disposed on the multi-layers stack and includes a second channel layer, a gate dielectric layer and a gate. The second channel layer is disposed on and electrically contacting to the first channel layer. The gate dielectric layer is disposed on the second channel layer and made of a material other than that for making the charge-trapping layer. The gate is disposed on the gate dielectric layer.
US10163925B2
An integrated circuit device includes a first and a second semiconductor regions, a first electrode provided above the first semiconductor region, a second electrode provided above the second semiconductor region, a first and a second interconnects. The first and the second semiconductor regions are arranged to be separated from each other in a first direction. Longitudinal directions of the first and second semiconductor regions are a second direction. Longitudinal directions of the first and second electrode are a third direction. The first and second interconnects extend in the first direction and are provided in a region including a region directly above the first electrode and a region directly above the second electrode. The first interconnect is connected to the first electrode. The second interconnect is connected to the second electrode.
US10163918B2
A semiconductor device includes a substrate including a plurality of active regions divided by a plurality of trenches, a plurality of tunnel insulating layer patterns formed over the active regions, a plurality of conductive film patterns formed over the tunnel insulating film patterns, a plurality of first isolation layers formed on sidewalls and bottom surfaces of the trenches, and a plurality of second isolation layers formed between the conductive film patterns.
US10163910B2
Described herein is a technique capable of suppressing the deviation in the characteristic of the semiconductor device. A method of manufacturing a semiconductor device may include: (a) receiving a data obtained by measuring a width of a first pillar between first grooves in a center region of a substrate and a width of a second pillar between second grooves in a peripheral region of the substrate; and (b) forming a width adjusting film on surfaces of the first grooves and the second grooves such that a sum of the width of the first pillar and a thickness of a first portion of the width adjusting film in the center region and a sum of the width of the second pillar and a thickness of a second portion of the width adjusting film in the peripheral region are within a predetermined range.
US10163909B2
A semiconductor memory device includes a semiconductor substrate having active areas and a trench isolation region between the active areas. The active areas extend along a first direction. Buried word lines extend along a second direction in the semiconductor substrate. Two of the buried word lines intersect with each of the active areas, separating each of the active areas into a digit line contact area and two cell contact areas. The second direction is not perpendicular to the first direction. A digit line contact is disposed on the digit line contact area. A storage node contact is disposed on each of the two cell contact areas. The digit line contact and the storage node contact are coplanar. At least one digit line extends along a third direction over a main surface of the semiconductor substrate. The at least one digit line is in direct contact with the digit line contact.
US10163907B2
Method of maintaining the state of semiconductor memory having electrically floating body transistor
Methods of maintaining a state of a memory cell without interrupting access to the memory cell are provided, including applying a back bias to the cell to offset charge leakage out of a floating body of the cell, wherein a charge level of the floating body indicates a state of the memory cell; and accessing the cell.
US10163904B1
A semiconductor device structure is provided. The semiconductor device structure includes a first circuit, a second circuit, and a dielectric dummy gate over a substrate. The first circuit includes a first N-type fin field-effect transistor (FinFET) and a first P-type fin field-effect transistor (FinFET). The second circuit includes a second N-type fin field-effect transistor (FinFET) and a second P-type fin field-effect transistor (FinFET) beside the second N-type FinFET. The dielectric dummy gate is positioned on a common boundary portion shared by the first circuit and the second circuit. The dielectric dummy gate includes a first portion and a second portion. The first portion is positioned between the first N-type FinFET and the second N-type FinFET and formed of a first strain material. The second portion is positioned between the first P-type FinFET and the second P-type FinFET and formed of a second strain material.
US10163898B2
An embodiment is a structure including a first fin over a substrate, a second fin over the substrate, the second fin being adjacent the first fin, an isolation region surrounding the first fin and the second fin, a first portion of the isolation region being between the first fin and the second fin, a gate structure along sidewalls and over upper surfaces of the first fin and the second fin, the gate structure defining channel regions in the first fin and the second fin, a gate seal spacer on sidewalls of the gate structure, a first portion of the gate seal spacer being on the first portion of the isolation region between the first fin and the second fin, and a source/drain region on the first fin and the second fin adjacent the gate structure.
US10163884B1
An IC includes an array of cells and a first set of endcap cells. The array of cells includes a first set of Mx layer power interconnects coupled to a first voltage, a first set of Mx layer interconnects, a second set of Mx layer power interconnects coupled to a second voltage source, and a second set of Mx layer interconnects. The first set of endcap cells includes first and second sets of Mx+1 layer interconnects. The first set of Mx+1 layer interconnects is coupled to the first set of Mx layer power interconnects and to the second set of Mx layer interconnects to provide a first set of decoupling capacitors. The second set of Mx+1 layer interconnects is coupled to the second set of Mx layer power interconnects and to the first set of Mx layer interconnects to provide a second set of decoupling capacitors.
US10163883B2
A layout method includes: selecting, by a processor or manual, a first layout device in a layout of an integrated circuit; selecting a second device abutting the first layout device at a boundary between the first layout device and the second layout device, wherein a conductive path is disposed across the boundary of the first layout device and the second layout device; and disposing a cut layer on the conductive path and nearby the boundary. The first layout device is a first layout pattern and the second layout device is a second layout pattern different from the first layout pattern.
US10163880B2
A layout includes a plurality of cells and at least one dummy gate electrode continuously extends across the cells. Since the dummy gate electrode is electrically conductive, the dummy gate electrode can be utilized for interconnecting the cells. That is, some signals may travel through the dummy gate electrode rather than through a metal one line or a metal two line. Therefore, an amount of metal one lines and/or metal two lines for interconnecting the cells can be reduced.
US10163868B2
A semiconductor device includes an insulating substrate having an insulating plate and a circuit plate; a semiconductor chip having a front surface provided with a gate electrode and a source electrode, and a rear surface fixed to the circuit plate; a printed circuit board facing the insulating substrate, and including a first metal layer and a second metal layer; a first conductive post having two ends electrically and mechanically connected to the gate electrode and the first metal layer; a second conductive post having two ends electrically and mechanically connected to the source electrode and the second metal layer; and a circuit impedance reducing element electrically connected between the gate electrode and the source electrode through the first conductive post and the second conductive post.
US10163864B1
The disclosure is directed to an integrated circuit stack and method of forming the same. In one embodiment, the integrated circuit stack may include: a plurality of vertically stacked wafers, each wafer including a back side and a front side, the back side of each wafer including a through-semiconductor-via (TSV) within a substrate, and the front side of each wafer including a metal line within a first dielectric, wherein the metal line is connected with the TSV within each wafer; and an inorganic dielectric interposed between adjacent wafers within the plurality of vertically stacked wafer; wherein the plurality of vertically stacked wafers are stacked in a front-to-back orientation such that the TSV on the back side of one wafer is electrically connected to the metal line on the front side of an adjacent wafer by extending through the inorganic dielectric interposed therebetween.
US10163861B2
A first package is bonded to a first substrate with first external connections and second external connections. The second external connections are formed using materials that are different than the first external connections in order to provide a thermal pathway from the first package. In a particular embodiment the first external connections are solder balls and the second external connections are copper blocks.
US10163853B2
Formation methods of a chip package are provided. The method includes bonding a first chip structure and a second chip structure over a substrate. The method also includes forming a release film to cover top surfaces of the first chip structure and the second chip structure. The method further includes forming a package layer to surround the first chip structure and the second chip structure after the formation of the release film. In addition, the method includes removing the release film such that the top surface of the first chip structure, the top surface of the second chip structure, and a top surface of the package layer are exposed.
US10163851B2
A package includes an Integrated Voltage Regulator (IVR) die, wherein the IVR die includes metal pillars at a top surface of the first IVR die. The package further includes a first encapsulating material encapsulating the first IVR die therein, wherein the first encapsulating material has a top surface coplanar with top surfaces of the metal pillars. A plurality of redistribution lines is over the first encapsulating material and the IVR die. The plurality of redistribution lines is electrically coupled to the metal pillars. A core chip overlaps and is bonded to the plurality of redistribution lines. A second encapsulating material encapsulates the core chip therein, wherein edges of the first encapsulating material and respective edges of the second encapsulating material are vertically aligned to each other. An interposer or a package substrate is underlying and bonded to the IVR die.
US10163845B2
Disclosed is a method of measuring a free air ball size during a wire bonding process of a wire bonder, which comprises a position sensor and a bonding tool for forming an electrical connection between a semiconductor device and a substrate using a bonding wire. Specifically, the method comprises the steps of: forming a free air ball from a wire tail of the bonding wire; using the position sensor to determine a positional difference between a first and a second position of the bonding tool with respect to a reference position, wherein the first position of the bonding tool is a position of the bonding tool with respect to the reference position when the free air ball contacts a conductive surface; and measuring the free air ball size based on the positional difference of the bonding tool as determined by the position sensor. A wire bonder configured to perform such a method is also disclosed.
US10163836B2
External electrical connectors and methods of forming such external electrical connectors are discussed. A method includes forming an external electrical connector structure on a substrate. The forming the external electrical connector structure includes plating a pillar on the substrate at a first agitation level affected at the substrate in a first solution. The method further includes plating solder on the external electrical connector structure at a second agitation level affected at the substrate in a second solution. The second agitation level affected at the substrate is greater than the first agitation level affected at the substrate. The plating the solder further forms a shell on a sidewall of the external electrical connector structure.
US10163821B2
Packaging devices and methods for semiconductor devices are disclosed. In some embodiments, a packaging device for a semiconductor device includes a packaging substrate including a semiconductor device mounting region. The packaging device includes a stress isolation structure (SIS) disposed on the packaging substrate proximate a portion of a perimeter of the semiconductor device mounting region.
US10163820B2
A method may include providing a chip carrier having a chip supporting region to support a chip, and a chip contacting region having at least one contact pad, the chip carrier being thinner in the chip contacting region such that a first thickness of the chip carrier at the at least one contact pad is smaller than a second thickness of the chip carrier in the chip supporting region. A disposing of the chip, having at least one contact protrusion, over the chip carrier, such that the at least one contact protrusion is arranged over the at least one contact pad may be included. In addition, a pressing of the chip against the chip carrier such that the at least one contact protrusion extends at least partially into the chip contacting region and is electrically contacted to the at least one contact pad may be included.
US10163819B2
A method for manufacturing a surface-mount type package whose face parallel with the semiconductor chip surface has a circular cross-section, is characterized by including at least the following steps in this order: a first step in which a semiconductor chip is bonded onto a circular support substrate; a second step in which the semiconductor chip is sealed with resin; a third step in which the resin covering the pads of the semiconductor chip is removed; a fourth step in which a rewiring layer is formed; and a fifth step in which bumps are formed. The method can provide a surface-mount type package for semiconductor chips which is resistant to failures caused by thermal stress.
US10163818B2
A package structure and method for forming the same are provided. The package structure includes a substrate and a semiconductor die formed over the substrate. The package structure also includes a package layer covering the semiconductor die and a conductive structure formed in the package layer. The package structure includes a first insulating layer formed on the conductive structure, and the first insulating layer includes monovalent metal oxide. A second insulating layer is formed between the first insulating layer and the package layer. The second insulating layer includes monovalent metal oxide, and a weight ratio of the monovalent metal oxide in the second insulating layer is greater than a weight ratio of the monovalent metal oxide in first insulating layer.
US10163808B2
A module includes a circuit package and a top external shield layer. The circuit package includes multiple electronic components on a substrate; at least one side shield structure located at a corresponding at least one side edge region of the circuit package and electrically connected to ground, the at least one side shield structure being positioned on the substrate or on a pad on the substrate; and a molded compound disposed over the substrate, the electronic components, and the at least one side shield structure. The top external shield layer is disposed on a top outer surface of the circuit package and is electrically connected to ground. The at least one side shield structure and the top external shield layer provide an external shield of the module configured to protect the circuit package from external electromagnetic radiation and environmental stress.
US10163803B1
Integrated fan-out packages and methods of forming the same are disclosed. An integrated fan-out package includes a first die, at least one through integrated fan-out via and a molding layer. The at least one through integrated fan-out via is aside the first die and includes a seed layer and a metal layer. The molding layer encapsulates the at least one through integrated fan-out via and the first die. Besides, the seed layer surrounds a sidewall of the metal layer and is between the metal layer and the molding layer.
US10163801B2
Structures and formation methods of a chip package are provided. The chip package includes a semiconductor die having a conductive feature and a protection layer surrounding the semiconductor die. The chip package also includes a dielectric layer arranged over the semiconductor die and the protection layer and partially covering the conductive feature. The conductive feature is arranged accessibly from the protection layer and the dielectric layer. The chip package further includes a conductive layer penetrating through the dielectric layer and electrically connected to the conductive feature of the semiconductor die. The conductive feature has a first portion covered by the dielectric layer and a second portion accessibly exposed from the dielectric layer, and the second portion has a surface roughness greater than that of the first portion.
US10163800B2
Package structures are provided. The package structure includes an integrated circuit die. The package structure also includes a package layer surrounding the integrated circuit die. There is an interface between the integrated circuit die and the package layer. The package structure further includes a redistribution structure below the integrated circuit die and the package layer. The redistribution structure includes active conductive lines electrically connected to the integrated circuit die. The redistribution structure also includes a dummy conductive line between the active conductive lines. The dummy conductive line extends across the interface.
US10163797B2
A plurality of high-k metal gate (HKMG) structures is formed over a substrate. The (HKMG) structures are separated by a plurality of gaps. The HKMG structures each include a first dielectric layer at an upper surface of the HKMG structure. The gaps are filled with a first conductive material. A portion of the first conductive material is removed in each of the gaps through an etching-back process. A metal oxide layer is formed using a spin-on deposition process. The metal oxide layer is formed over the (HKMG) structures and over the first conductive material. A second dielectric layer is formed over the metal oxide layer. An opening is etched in the second dielectric layer. The opening is etched through the second dielectric layer and through the metal oxide layer. The opening is filled with a second conductive material.
US10163795B2
The present disclosure relates to an integrated circuit device and an associated method of formation. The integrated circuit device includes a substrate, and a conductive metal interconnect line arranged within a dielectric material disposed over the substrate. An interfacial layer is in contact with an upper surface of the conductive metal interconnect line. An upper dielectric layer is arranged over the interfacial layer. A middle dielectric layer is arranged between the upper dielectric layer and the interfacial layer.
US10163776B2
Disclosed herein is a capacitive element formed by multilayer wirings, wherein a total capacitance, intralayer capacitance and interlayer capacitance are calculated for a plurality of device structures by changing parameters relating to the multilayer wirings in an integrated circuit, a device structure is identified, from among the plurality of device structures, whose difference in the total capacitance between the device structures is equal to or less than a predetermined level and at least either of whose ratio of the intralayer capacitance to the total capacitance or ratio of the interlayer capacitance to the total capacitance satisfies a predetermined condition, and the parameters of the device structure satisfying the predetermined condition are determined as the parameters of the multilayer wirings.
US10163774B2
A die and a substrate are provided. The die comprises at least one integrated circuit chip, and the substrate comprises first and second subsets of conductive pillars extending at least partially therethrough. Each of the first subset of conductive pillars comprises a protrusion bump pad protruding from a surface of the substrate, and the second subset of conductive pillars each partially form a trace recessed within the surface of the substrate. The die is coupled to the substrate via a plurality of conductive bumps each extending between one of the protrusion bump pads and the die.
US10163768B2
A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes: a substrate comprising a recess portion filled with a conductive material; a conductive trace overlying and contacting the conductive material; a conductive pillar disposed on the conductive trace and over the recess portion of the substrate; and a semiconductor chip disposed on the conductive pillar.
US10163761B2
A power semiconductor device comprises a substrate; and power semiconductor components disposed on and connected thereto. The device includes a housing part with a housing wall having a first cutout. The device has, for making electrical contact therewith, a unitary load connection element which passes through the first cutout in an X direction, is electrically conductive, and has an outer connection section disposed outside the housing part and an inner connection section disposed within the housing part. A first bush which has an internal thread running in the X direction is rotationally fixed and movable in the X direction in the housing wall. The first outer connection section has a second cutout aligned with the first bush. The load connection element has a first holding element disposed near the first cutout, the holding element engaging in a groove in the housing wall which runs perpendicular to the X direction.
US10163758B1
Present disclosure provides a semiconductor structure, including a semiconductor substrate having an active side, an interconnect layer over the active side of the semiconductor substrate, and a through substrate via (TSV) extending from the semiconductor substrate to the first metal layer. The interconnect layer includes a first metal layer closest to the active side of the semiconductor substrate, a thickness of the first metal layer is lower than 1 micrometer, and a dimension of a continuous metal feature of the first metal layer is less than 2 micrometer from a top view perspective. The continuous metal feature is cut off by a first dielectric feature. Present disclosure also provides a method for manufacturing the semiconductor structure described herein.
US10163743B2
An air cavity package includes a flange and a pedestal extending upward from the flange. A dielectric frame is joined to the flange and surrounds the pedestal. The semiconductor die is placed on the pedestal, which reduces the length of the wires joining the die to the leads of the air cavity package.
US10163733B2
A method provides a design layout having a pattern of features. The design layout is transferred onto a substrate on a semiconductor substrate using a mask. A scanning parameter is determined based on the design layout. An image of the substrate is generated using the determined scanning parameter. A substrate defect is identified by comparing a first number of closed curves in a region of the image and a second number of polygons in a corresponding region of the design layout.
US10163732B2
A substrate processing chamber, having a processing surface, includes a guide fixed in place relative to the substrate processing chamber and a movable pyrometer connected to the guide. The movable pyrometer is movable along a radial axis that extends approximately between a center of the processing surface and an outer surface of the processing surface. The movable pyrometer is operable to monitor temperatures inside the substrate processing chamber along the radial axis.
US10163726B2
In accordance with some embodiments, a device includes first and second p-type transistors. The first transistor includes a first channel region including a first material of a first fin. The first transistor includes first and second epitaxial source/drain regions each in a respective first recess in the first material and on opposite sides of the first channel region. The first transistor includes a first gate stack on the first channel region. The second transistor includes a second channel region including a second material of a second fin. The second material is a different material from the first material. The second transistor includes third and fourth epitaxial source/drain regions each in a respective second recess in the second material and on opposite sides of the second channel region. The second transistor includes a second gate stack on the second channel region.
US10163722B2
A semiconductor device includes a substrate; first and second fins over the substrate and extending lengthwise generally along a first direction; first and second gate stacks over the substrate and the first and second fins respectively; and a first isolation structure disposed between the first and second fins and extending lengthwise generally along a second direction perpendicular to the first direction, wherein the first isolation structure is adjacent to a first source/drain (S/D) region in the first fin and adjacent to a second S/D region in the second fin.
US10163718B2
In a method of manufacturing a semiconductor device, a dummy gate structure is formed over a substrate. A first insulating layer is formed over the dummy gate structure. The dummy gate structure is removed so as to form a gate space in the first insulating layer. A first conductive layer is formed in the gate space so as to form a reduced gate space. The reduced gate space is filled with a second conductive layer made of a different material from the first conductive layer. The filled first conductive layer and the second conductive layer are recessed so as to form a first gate recess. A third conductive layer is formed over the first conductive layer and the second conductive layer in the first gate recess. After recessing the filled first conductive layer and the second conductive layer, the second conductive layer protrudes from the first conductive layer.
US10163717B2
A semiconductor device includes a substrate, a first insulating structure, a second insulating structure, at least one first active semiconductor fin, and at least one second active semiconductor fin. The first insulating structure and the second insulating structure are disposed on the substrate. The first active semiconductor fin is disposed on the substrate and has a protruding portion protruding from the first insulating structure. The second active semiconductor fin is disposed on the substrate and has a protruding portion protruding from the second insulating structure. The protruding portion of the first active semiconductor fin and the protruding portion of the second active semiconductor fin have different heights.
US10163715B2
A FinFET device and a method of forming the same are provided. A method includes forming a fin over a substrate. An isolation region is formed adjacent the fin. A dummy gate structure is formed over the fin. The fin adjacent the dummy gate structure is recessed to form a first recess. The first recess has a U-shaped bottom surface. The U-shaped bottom surface is below a top surface of the isolation region. The first recess is reshaped to form a reshaped first recess. The reshaped first recess has a V-shaped bottom surface. At least a portion of the V-shaped bottom surface comprises one or more steps. A source/drain region is epitaxially grown in the reshaped first recess.
US10163709B2
A semiconductor device and method of manufacture are provided. In an embodiment a first semiconductor device and a second semiconductor device are formed within a semiconductor wafer and a scribe region between the first semiconductor device and the second semiconductor device is patterned. A singulation process is then utilized within the scribe region to singulate the first semiconductor device from the second semiconductor device. The first semiconductor device and the second semiconductor device are then bonded to a second semiconductor substrate and thinned in order to remove extension regions from the first semiconductor device and the second semiconductor device.
US10163706B2
A device includes a substrate, and an alignment mark including a conductive through-substrate via (TSV) penetrating through the substrate.
US10163705B2
An interconnect structure for an integrated circuit, such as a three dimensional integrated circuit (3DIC), and a method of forming the same is provided. An example interconnect structure includes a substrate, a through via extending through the substrate, and a liner disposed between the substrate and the through via. The substrate includes a tapered profile portion. The tapered profile portion abuts the liner.
US10163697B2
Disclosed is a method of forming back end of the line (BEOL) metal levels with improved dielectric capping layer to metal wire adhesion. The method includes process step(s) designed to address dielectric capping layer to metal wire adhesion, when the metal wire(s) in a given metal level are relatively thick. These process step(s) can include, for example: (1) selective adjustment of the deposition tool used to deposit the dielectric capping layer onto metal wires based on the pattern density of the metal wires in order to ensure that those metal wires actually achieve a temperature between 360° C.-400° C.; and/or (2) deposition of a relatively thin dielectric layer on the dielectric capping layer prior to formation of the next metal level in order to reduce the tensile stress of the metal wire(s) below without causing delamination. Also disclosed is an IC chip formed using the above-described method.
US10163692B2
Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a substrate having a first top surface, and an interconnection line over the first top surface of the substrate. The interconnection line has a sidewall. The semiconductor device structure also includes a first spacer over the sidewall of the interconnection line. The first spacer has a first concave surface which concaves towards the sidewall of the interconnection line. The semiconductor device structure further includes a dielectric layer covering the substrate, the interconnection line and the first spacer.
US10163689B2
A semiconductor device is disclosed, including a plurality of conductive features disposed over a substrate. A dielectric layer separates the conductive features. A conductive line is provided, connecting a subset of the conductive features. The conductive line includes a line-like portion and a line-end portion.
US10163688B2
Among other things, one or more interconnect structures and techniques for forming such interconnect structures within integrated circuits are provided. An interconnect structure comprises one or more kinked structures, such as metal structures or via structures, formed according to a kinked profile. For example, the interconnect structure comprises a first kinked structure having a first tapered portion and a second kinked structure having a second tapered portion. The first tapered portion and the second tapered portion are both situated at an interface between two layers. Current leakage at the interface is mitigated because a length of the interface corresponds to a distance between the first tapered portion and the second tapered portion that is relatively larger than if the first kinked structure and the second kinked structure were merely formed according to a non-tapered shape.
US10163682B2
The present disclosure relates to a process for the manufacture of a high resistivity semiconductor substrate, comprising the following stages: providing a first substrate with an in-depth weakened layer; providing a second substrate with a layer of an oxide at the surface; attaching the first substrate to the second substrate so as to form a compound substrate comprising a layer of buried oxide; and cleaving the compound substrate at the level of the weakened layer. The process additionally comprises at least one stage of stabilization, in particular, a stabilization heat treatment, of the second substrate with the layer of oxide before the stage of cleaving at the level of the weakened layer.
US10163676B2
A apparatus includes a susceptor and a non-reactive gas source. The susceptor has through holes and a wafer support surface. Each through hole includes a lift pin and a lift pin head. The lift pin has a vertical degree of motion in the through hole to lift up or place a wafer on the susceptor. The lift pin head has at least one flow channel structure running from its first surface at least partially exposed to a bottom side of the susceptor through its second surface exposed to a top side of the susceptor wherein the lift pin. The non-reactive gas source is configured to flow a gas to a backside of the wafer through the flow channel structure through the bottom side of the susceptor.
US10163673B2
The embodiments of the present invention relate to semiconductor device manufacturing, and more particularly, a method of temporarily bonding a semiconductor wafer to a wafer carrier with a multi-layered contact layer as well as a structure. A method is disclosed that includes: forming a first layer on a surface of a semiconductor wafer; forming a second layer on the first layer; bonding a perforated carrier to the second layer; and removing the semiconductor wafer from the perforated carrier. The first layer may be composed of an adhesive. The second layer may be composed of a material having a higher outgassing temperature than the first layer.
US10163668B2
A heater system includes a heater assembly, an imaging device and a control system. The heater assembly includes a plurality of heating zones. The imaging device acquires an image of the heater assembly. The control system determines variations in the plurality of heating zones based on the thermal image.
US10163659B1
A FinFET and a method of forming the same are provided. The FinFET includes a substrate, a buffer layer, an insulating layer, a fin and a gate. A buffer layer is disposed over the substrate, and includes a recess without penetrating the buffer layer. The insulating layer is disposed over the buffer layer, and includes a plurality of isolation structures and a trench between the isolation structures. The fin is disposed in the recess of the buffer layer and the trench of the insulating layer. The gate is disposed across the fin.
US10163640B1
A method of forming a gate isolation plug for FinFETs includes forming an elongated gate, forming first and second spacers in contact with first and second sidewalls of the elongated gate, separating the elongated gate into first and second gate portions using first and second etching steps, and forming a gate isolation plug between the first and second gate portions, wherein a length of the gate isolation plug is greater than a length of either of the first or second gate portions.
US10163638B2
High-voltage semiconductor devices are provided. The high-voltage semiconductor device includes a substrate having a first conductive type and an epitaxial layer having a second conductive type disposed on the substrate. The epitaxial layer includes a high-voltage unit, a low-voltage unit disposed around the high-voltage unit and a level-shift unit disposed between the high-voltage unit and the low-voltage unit. The level-shift unit includes a source region, a drain region having disposed between the source region and the high-voltage unit, wherein the drain region is electrically connected to the high-voltage unit by a drain electrode disposed above the drain region. The level unit includes a gate electrode disposed between the source region and the drain region. The high-voltage semiconductor device also includes an isolation structure disposed between the high-voltage unit and the low-voltage unit, and the isolation structure is disposed directly under the drain electrode.
US10163634B2
Various patterning methods involved with manufacturing semiconductor device structures are disclosed herein. A method for forming a semiconductor device structure (for example, a conductive line) includes forming a first hard mask layer and a second hard mask layer over a dielectric layer. The first hard mask layer has a first opening, and the second hard mask layer has a first trench connected to the first opening. A filling layer is formed in the first opening, where the filling layer has a second opening and a third opening. The first hard mask layer and the dielectric layer are removed through the second opening and the third opening to form a second trench and a third trench in the dielectric layer. The first hard mask layer, the second hard mask layer, and the filling layer can be removed. A conductive layer is formed in the second trench and the third trench.
US10163630B2
The present disclosure generally relates to methods for removing contaminants and native oxides from substrate surfaces. The method includes exposing a surface of the substrate to first hydrogen radical species, wherein the substrate is silicon germanium having a concentration of germanium above about 30%, then exposing the surface of the substrate to a plasma formed from a fluorine-containing precursor and a hydrogen-containing precursor, and then exposing the surface of the substrate to second hydrogen radical species.
US10163625B2
There is provided a method for manufacturing a semiconductor device, including: providing a substrate with an oxide film formed on a surface thereof; pre-processing a surface of the oxide film; and forming a nitride film containing carbon on the surface of the oxide film which has been pre-processed, by performing a cycle a predetermined number of times, the cycle including non-simultaneously performing: supplying a precursor gas to the substrate; supplying a carbon-containing gas to the substrate; and supplying a nitrogen-containing gas to the substrate, or by performing a cycle a predetermined number of times, the cycle including non-simultaneously performing: supplying a precursor gas to the substrate; and supplying a gas containing carbon and nitrogen to the substrate, or by performing a cycle a predetermined number of times, the cycle including non-simultaneously performing: supplying a precursor gas containing carbon to the substrate; and supplying a nitrogen-containing gas to the substrate.
US10163624B2
Semiconductor structures are provided. The semiconductor structure includes a substrate and a first fin structure and a second fin structure formed over the substrate. The semiconductor structure further includes an isolation structure formed around the second fin structure and covering the first fin structure and a gate structure formed over the first fin structure and the second fin structure. The semiconductor structure further includes the first fin structure has a first height and the second fin structure has a second height higher than the first height, and the gate structure and the first fin structure are separated by the isolation structure.
US10163612B2
An end-block for rotatably carrying a sputtering target tube and for rotatably restraining a magnet bar inside the sputtering target tube includes a receptacle for receiving a magnet bar fitting. The receptacle comprises a first part of a signal connector arranged to receive a second part of a signal connector from the magnet bar fitting, and allow a signal connector between the end-block and the magnet bar to be formed. The end-block is adapted for providing protection means to the signal connector for protecting it from degradation, destruction or interference of a power and/or data signal transmitted between the end-block and the magnet bar, due to surrounding cooling fluid and/or surrounding high energy fields. The disclosure provides a corresponding magnet bar, and a method for adjusting a magnetic configuration of a magnet bar in a cylindrical sputtering apparatus.
US10163610B2
An edge ring assembly for a plasma processing chamber is provided, including: an edge ring configured to surround an electrostatic chuck (ESC) that is configured for electrical connection to a first RF power supply, the ESC having a top surface for supporting a substrate and an annular step surrounding the top surface, the annular step defining an annular shelf that is lower than the top surface; an annular electrode disposed below the edge ring in the annular step and above the annular shelf; a dielectric ring disposed below the annular electrode for isolating the annular electrode from the ESC, the dielectric ring positioned in the annular step over the annular shelf; and, a plurality of insulated connectors disposed through the ESC and through the dielectric ring, each of the plurality of insulated connectors providing electrical connection between a second RF power supply and the annular electrode.
US10163608B2
The present invention provides novel plasma sources useful in the thin film coating arts and methods of using the same. More specifically, the present invention provides novel linear and two dimensional plasma sources that produce linear and two dimensional plasmas, respectively, that are useful for plasma-enhanced chemical vapor deposition. The present invention also provides methods of making thin film coatings and methods of increasing the coating efficiencies of such methods.
US10163602B2
Provided is an ion beam system including a gas field ionization ion source which can obtain a high current sufficient for processing and stabilize an ion beam current. The ion beam system includes a gas field ionization ion source which includes: a vacuum vessel; an emitter tip holder disposed in the vacuum vessel; an emitter tip connected to the emitter tip holder; an extraction electrode opposed to the emitter tip; a gas supply portion for supplying a gas to the emitter tip; and a cold transfer member disposed in the vacuum vessel and transferring cold energy to the emitter tip holder. The cold transfer member has its surface covered with a heat insulating material in order to prevent the gas condensation.
US10163600B2
A rotatable anode target for an X-ray tube (1) of the present invention includes a metallic disc (2) which includes a first crystal structure; a metallic cylinder (3) which is joined with the metallic disc and includes a second crystal structure, where a first average aspect ratio of first crystal grains positioning at a first region within 2 mm from an interface between the metallic disc and the metallic cylinder is less than 2, and a second average aspect ratio of second crystal grains positioning at a second region within 2 mm from the interface is 2 or more and 8 or less. It is thereby possible to provide an X-ray tube target which has high heat release performance and where thermal deformation is difficult to occur.
US10163589B2
An adapter assembly configured to be coupled to a surgical loading unit includes a switch, an elongated member, and an annular member. The switch is configured to be toggled in response to the surgical loading unit being coupled to the adapter assembly. The elongated member is in communication with the switch and is resiliently biased in a distal direction toward a locking position in which the switch is toggled. The annular member is disposed adjacent the elongated member and is rotatable between a first orientation, in which the annular member prevents distal movement of the elongated member, and a second orientation, in which the elongated member moves distally to toggle the switch.
US10163572B2
A ceramic-wound-capacitor includes a first-electrically-conductive-layer, a dielectric-layer, a second-electrically-conductive-layer, and a protective-coating. The dielectric-layer is formed of lead-lanthanum-zirconium-titanate (PLZT). The protective-coating has a thickness of less than ten micrometers (10 μm) and provides electrical isolation between the first-electrically-conductive-layer and the second-electrically-conductive-layer of the ceramic-wound-capacitor. A method for fabricating the ceramic-wound-capacitor includes the steps of feeding a carrier-strip, depositing a sacrificial layer, depositing a first-electrically-conductive-layer, depositing a dielectric-layer, and depositing a second-electrically-conductive-layer to form an arrangement coupled to the carrier-strip by the sacrificial-layer, separating the arrangement from the carrier-strip and sacrificial-layer, creating an exposed-surface of the first-electrically-conductive-layer, applying a protective-coating to the exposed-surface of the first-electrically-conductive-layer, winding the arrangement with the protective-coating to form a ceramic-wound-capacitor, where the protective-coating is in direct contact with the first-electrically-conductive-layer and the second-electrically-conductive-layer of the ceramic-wound-capacitor.
US10163570B2
An electrical double layer capacitor having electrolyte-containing layer between a first polarizable electrode layer and a second polarizable electrode layer. An insulating adhesive portion adheres to a first current collector and a second current collector which at least partially face each other with the electrolyte-containing layer interposed therebetween. The insulating adhesive portion 15 extends around the first and second polarizable electrode layers and the electrolyte-containing layer. A thickness of the electrolyte-containing layer is larger than a difference between a thickness of the insulating adhesive portion and thicknesses of the first and second polarizable electrode layers.
US10163564B2
Disclosed are a wireless power transmitter and a method of controlling power thereof. A wireless power transmitter includes a power supply device to supply AC power to the wireless power transmitter; and a transmission coil to transmit the AC power to a reception coil of a wireless power receiver by resonance. The wireless power transmitter controls transmission power to be transmitted to the wireless power receiver based on a coupling state between the transmission coil and the reception coil.
US10163563B2
Provided is a reactor in which an accessory member that is attached to the reactor is integrated with an assembly. The reactor includes an assembly of a coil having a winding portion and a magnetic core and an accessory member that is attached to the assembly. In this reactor, an outer core portion of the magnetic core is made of a composite material obtained by dispersing soft magnetic powder in a resin, the outer core portion protruding from the winding portion, and the accessory member includes an embedded portion that is embedded in the outer core portion and a functional portion that protrudes outward from the outer core portion.
US10163561B1
A distributed planar inductor is provided with energy storage components featuring high energy storage density, multilayer winding and low copper losses. The inductor includes a magnetic core with a plurality of vertically oriented posts, a plurality of horizontally oriented plates coupled to define an interior, and a conductive winding extending through the interior. The vertical posts each include a plurality of energy storage elements coplanar in orientation with respect to the winding and having a substantially two dimensional structure. The conductive winding may comprise co-planar winding tracks extending through the interior, for example vertically coupled in parallel. A set of co-planar winding tracks may correspond to respective layers in a multilayer printed circuit board, and for example may comprise printed circuit board tracks vertically interconnected by vias extending there-through.
US10163553B2
Provided is a resistor including a first electrode, a second electrode, and a resistive element disposed between the first and second electrodes. Each of the first and second electrodes includes a main electrode portion and a narrow electrode portion with a narrower width than that of the main electrode portion. The resistive element is disposed between the two narrow electrode portions.
US10163546B2
A field control device for a high-voltage system includes a shielding element for field control, which can be connected to an electrical conductor of the high-voltage system in an electrically conductive manner and, when connected to the conductor, at least partly delimits a weak-electric-field spatial region. A cooling body, which can be connected to the electrical conductor in a thermally conductive manner and which is disposed within the weak-field spatial region, has an outer surface area which is greater than an outer surface area of the shielding element. A high-voltage system having the field control device is also provided.
US10163540B2
A process for producing a highly conducting film of conductor-bonded graphene sheets that are highly oriented, comprising: (a) preparing a graphene dispersion or graphene oxide (GO) gel; (b) depositing the dispersion or gel onto a supporting solid substrate under a shear stress to form a wet layer; (c) drying the wet layer to form a dried layer having oriented graphene sheets or GO molecules with an inter-planar spacing d002 of 0.4 nm to 1.2 nm; (d) heat treating the dried layer at a temperature from 55° C. to 3,200° C. for a desired length of time to produce a porous graphitic film having pores and constituent graphene sheets or a 3D network of graphene pore walls having an inter-planar spacing d002 less than 0.4 nm; and (e) impregnating the porous graphitic film with a conductor material that bonds the constituent graphene sheets or graphene pore walls to form the conducting film.
US10163535B2
Biomass (e.g., plant biomass, animal biomass, and municipal waste biomass) is processed to produce useful intermediates and products, such as energy, fuels, foods or materials. For example, systems and methods are described that can be used to treat feedstock materials, such as cellulosic and/or lignocellulosic materials, while cooling equipment and the biomass to prevent overheating and possible distortion and/or degradation. The biomass is conveyed by a conveyor, which conveys the biomass under an electron beam from an electron beam accelerator. The conveyor can be cooled with cooling fluid. The conveyor can also vibrate to facilitate exposure to the electron beam. The conveyor can be configured as a trough that can be optionally cooled.
US10163533B2
A sealing device is provided to form a sealed region about one or more surfaces to be treated. The sealing device has an open end with a rim configured to matingly engage a treatment surface. The sealing device is braced both vertically and laterally, and the sealed region is flooded and pressurized. A peening nozzle and manipulating tooling are positioned within an interior volume of the sealing device. Pressurized fluid is ejected from the nozzle causing the formation of cavitation bubbles. The nozzle flow causes the cavitation bubbles to settle on the surfaces to be treated. The collapsing impact of the cavitation bubbles imparts compressive stress in the materials of the treatment surfaces.
US10163525B2
A test apparatus includes a device under test (DUT) configured to exchange data using a serial interface protocol and a test controller configured to receive a binary vector corresponding to a physical layer of the serial interface protocol from an external device and to buffer and transmit the received binary vector to the DUT.
US10163516B2
A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate. The semiconductor device structure includes a gate stack over the semiconductor substrate. The gate stack includes a first insulating layer, a charge trapping structure, a second insulating layer, and a gate electrode. The first insulating layer separates the semiconductor substrate from the charge trapping structure. The charge trapping structure is between the first insulating layer and the second insulating layer. The gate electrode is over the second insulating layer. The charge trapping structure includes a first layer and a second layer. The first layer includes zinc oxide, tin dioxide, titanium oxide, zinc tin oxide, indium oxide, indium zinc oxide, indium gallium zinc oxide, zinc oxynitride, tin oxynitride, titanium oxynitride, zinc tin oxynitride, indium oxynitride, indium zinc oxynitride, or indium gallium zinc oxynitride. The second layer includes nickel oxide, tin oxide, copper oxide, nickel oxynitride, tin oxynitride, or copper oxynitride. The semiconductor device structure includes a first doped region and a second doped region in the semiconductor substrate and on two opposite sides of the gate stack.
US10163506B2
Disclosed herein is a memory cell including a memory element and a selector device. The memory cell may be programmed with a programming pulse having a first polarity and read with a read pulse having a second polarity. The memory cell may be programmed with a programming pulse having first and second portions. The first and second portions may have different magnitudes and polarities. The memory cell may exhibit reduced voltage drift and/or threshold voltage distribution. Described herein is a memory cell that acts as both a memory element and a selector device. The memory cell may be programmed with a programming pulse having first and second portions. The first and second portions may have different magnitudes and polarities.
US10163501B2
Apparatuses, memories, and methods for decoding memory addresses for selecting access lines in a memory are disclosed. An example apparatus includes an address decoder circuit coupled to first and second select lines, a polarity line, and an access line. The first select line is configured to provide a first voltage, the second select line is configured to provide a second voltage, and the polarity line is configured to provide a polarity signal. The address decoder circuit is configured to receive address information and further configured to couple the access line to the first select line responsive to the address information having a combination of logic levels and the polarity signal having a first logic level and further configured to couple the access line to the second select line responsive to the address information having the combination of logic levels and the polarity signal having a second logic level.
US10163497B2
A three dimensional dual-port bit cell generally comprises a first portion disposed on a first tier, wherein the first portion includes a plurality of port elements. The dual-port bit cell also includes a second portion disposed on a second tier that is vertically stacked with respect to the first tier using at least one via, wherein the second portion includes a latch.
US10163495B2
A static random access memory (SRAM) device is provided in accordance with some embodiments. The SRAM device comprises a plurality of two-port SRAM arrays, which comprise a plurality of two-port SRAM cells. Each two-port SRAM cell comprises a write port portion, a read port portion, a first plurality of metal lines located in a first metal layer, a second plurality of metal lines located in a second metal layer, a third plurality of metal lines located in a third metal layer a plurality of edge cells, a plurality of well strap cells, and a plurality of jumper structures. Each jumper structure comprises first, second, and third metal landing pads located in the second metal layer and electrically connecting metal lines of the first and third metal layers.
US10163491B2
A memory circuit includes first and second memory cells. The first memory cell has an access port having a pass gate. The second memory cell also has an access port having a pass gate. The first and second memory cells abut one another along a column direction. The circuit includes at least one conductive structure over the first and second memory cells. The conductive structure may be two interconnected conductive lines. The conductive structure extends along a row direction in a conductive layer and is electrically coupled to the gate terminals of the pass gates.
US10163486B1
A semiconductor device includes a clock gating tree comprising a first clock gating stage and a second clock gating stage. The first clock gating stage is configured to receive an activate detection signal and to activate clocking events in the second clock gating stage in response to the activate detection signal. The clocking events are not activated in the absence of the activate detection signal.
US10163482B2
Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A ground reference scheme may be employed in a digit line voltage sensing operation. A positive voltage may be applied to a memory cell; and after a voltage of the digit line of the cell has reached a threshold, a negative voltage may be applied to cause the digit line voltages to center around ground before a read operation. In another example, a first voltage may be applied to a memory cell and then a second voltage that is equal to an inverse of the first voltage may be applied to a reference capacitor that is in electronic communication with a digit line of the memory cell to cause the digit line voltages to center around ground before a read operation.
US10163481B1
Methods, systems, and devices for offset cancellation for latching in memory devices are described. A memory device may include a sense component comprising a first and second transistor. In some cases, a memory device may further include a first capacitor coupled to the first transistor and a second capacitor coupled to the second transistor and a first switching component coupled between a voltage source and the first capacitor and the second capacitor. For example, the first switching component may be activated, a reference voltage may be applied to the sense component, and the first switching component may then be deactivated. In some examples, a voltage offset may be measured across both the first and the second capacitor.
US10163477B1
A memory array having a first port and a second port is disclosed. The memory array includes: a first memory cell, wherein access to the first memory cell through the first port is controlled by a first word line, and access to the first memory cell through the second port is controlled by a second word line; a second memory cell, wherein access to the second memory cell through the first port is controlled by the first word line, and access to the second memory cell through the second port is controlled by the second word line; and a disturb detector, used to generate a disturb detected signal for indicating whether the first memory cell and the second memory cell are accessed at a same time. A memory array having a write assistor is also disclosed.
US10163471B2
A memory controller circuitry includes a timestamp circuitry and a demarcation voltage (VDM) selection circuitry. The timestamp circuitry is to capture a global timer index from a global timer having a granularity, G. The timestamp circuitry is further to fetch a timestamp for a memory block that includes a group of sub-blocks that includes a target sub-block. The demarcation voltage (VDM) selection circuitry is to fetch a combined count from a count store. The combined count represents a combined state. The combined state includes a target individual state of the target sub-block and a respective individual state of each of at least one other sub-block of the group of sub-blocks included in the memory block.
US10163468B2
A processor includes N-bit registers and a decode unit to receive a multiple register memory access instruction. The multiple register memory access instruction is to indicate a memory location and a register. The processor includes a memory access unit coupled with the decode unit and with the N-bit registers. The memory access unit is to perform a multiple register memory access operation in response to the multiple register memory access instruction. The operation is to involve N-bit data, in each of the N-bit registers comprising the indicated register. The operation is also to involve different corresponding N-bit portions of an M×N-bit line of memory corresponding to the indicated memory location. A total number of bits of the N-bit data in the N-bit registers to be involved in the multiple register memory access operation is to amount to at least half of the M×N-bits of the line of memory.
US10163465B1
A data receiver for a double data rate (DDR) memory includes a first stage circuit and a second stage circuit. The first stage circuit is deployed for receiving a single-ended signal from the DDR memory and converting the single-ended signal into a pair of differential signals. The second stage circuit, coupled to the first stage circuit, is deployed for receiving the differential signals from the first stage circuit and converting the differential signals into an output signal. Both of the first stage circuit and the second stage circuit are implemented in a core voltage domain.
US10163462B1
An exemplary write method disclosed herein includes receiving a request to write data to a consecutive sequence of logical block addresses (LBAs) that is the mapped to a non-contiguous sequence of data tracks on a storage medium, and writing the data of the consecutive sequence of LBAs to a non-contiguous sequence of data tracks on the storage medium and according to a consecutive track order.
US10163461B2
A magazine management device stores a plurality of magazines in which a plurality of optical discs is housed. The magazine management device includes a case that supports the plurality of magazines, a plurality of partitions that divides the case so as to form a plurality of regions in which the magazines can be stored one by one, an antenna that transmits a radio wave for asking a radio identifier provided to the magazine for a response and receives a radio wave of the response transmitted from the radio identifier, and an arithmetic processor that receives information obtained from the radio wave of the response received by the antenna.
US10163460B1
Techniques for management of movable devices are disclosed. A system receives a request for an operation associated with a position on a rail. The system selects a component on the rail to execute the operation. The system identifies a rail segment that extends from the component's initial position to the position associated with the operation. The system requests a reservation of that rail segment. If the reservation is obtained, then the system applies electrical signals to move the component along the rails segment to the rail position associated with the operation. The system may also identify one or more other components, physical cells, etc. to reserve, in order to complete the operation.
US10163458B2
According to one embodiment, a magnetic disk device includes a memory, a disk including track groups each including overlapping tracks, a head including a write head, and a read head, and a controller configured to write first position data, including a first position error of the write head with respect to a first target track, to the memory and a second recording area subsequent to a first recording area to which first data is written, when writing the first data to the track groups, to read the first position data from the memory or the second recording area when adding data after writing the first data, and to control a position of the write head based on the first position data.
US10163457B2
According to one embodiment, a method of manufacturing a lift tab of a suspension assembly, includes: forming a first mask on a first surface of a plate-shaped base material; forming a second mask smaller than the first mask by a width less than or equal to a plate thickness of the base material, on a second surface of the base material, which is on an opposite side to the first surface, to oppose the first mask; etching the base material from both surface sides through the first mask and the second mask, to cut out the base material; and subjecting the cut-out base material to a bending process to form the lift tab.
US10163446B2
This disclosure falls into the field of audio coding, in particular it is related to the field of spatial audio coding, where the audio information is represented by multiple audio objects including at least one dialog object. In particular the disclosure provides a method and apparatus for enhancing dialog in a decoder in an audio system. Furthermore, this disclosure provides a method and apparatus for encoding such audio objects for allowing dialog to be enhanced by the decoder in the audio system.
US10163445B2
Provided is an apparatus and method of encoding and decoding multiple channel signals based upon phase information and one or more residual signals.
US10163441B2
A method for receiving processed information at a remote device is described. The method includes transmitting from the remote device a verbal request to a first information provider and receiving a digital message from the first information provider in response to the transmitted verbal request. The digital message includes a symbolic representation indicator associated with a symbolic representation of the verbal request and data used to control an application. The method also includes transmitting, using the application, the symbolic representation indicator to a second information provider for generating results to be displayed on the remote device.
US10163438B2
An electronic device includes a microphone that receives an audio signal that includes a spoken trigger phrase, and a processor that is electrically coupled to the microphone. The processor measures characteristics of the audio signal, and determines, based on the measured characteristics, whether the spoken trigger phrase is acceptable for trigger phrase model training. If the spoken trigger phrase is determined not to be acceptable for trigger phrase model training, the processor rejects the trigger phrase for trigger phrase model training.
US10163426B2
A bass drum damper and a bass drum are provided. The bass drum damper includes a sound insulating plate that covers a batter head of an acoustic bass drum generating a percussive sound when a beater of a foot pedal percusses a predetermined percussion location. The sound insulating plate includes a contact portion having an opening portion open for the percussion location for the beater and is in contact with the batter head, and a fixing portion provided at a circumferential edge of the contact portion and fixed to a hoop applying a tensile force to the batter head, or the batter head. At least a part of the contact portion which is in contact with the batter head when not being percussed is separated from the batter head at a time of percussing of the beater and is brought into contact with the batter head again after percussing.
US10163423B2
A control method of a display includes a statistics circuit, a backlight determining circuit and a backlight control circuit. The display includes a backlight module having a maximum luminance. The statistics module receives frame, and generates luminance statistical information of a plurality of blocks included in the frame. The backlight determining circuit determines a backlight intensity corresponding to each of the blocks according to the luminance statistical information of the blocks and the maximum luminance. At least one of the backlight intensities corresponding to the blocks is greater than a normal luminance, which is a backlight intensity corresponding to one of the blocks when a maximum power is evenly distributed on light emitting elements of the display. The backlight control circuit controls the luminance of the backlight module according to the backlight intensities.
US10163417B2
A display panel driving apparatus includes a data driving part, a gate driving part and an off voltage controlling part. The data driving part is configured to output a data signal to a data line of a display panel. The gate driving part is configured to output a gate signal to a gate line of the display panel. The off voltage controlling part is configured to receive a first off voltage and a second off voltage applied to the gate driving part to generate the gate signal, measure a leakage current of the gate driving part, and control the first off voltage based on the leakage current. Thus, display quality of a display apparatus including the gate driving part may be enhanced.
US10163414B2
A GOA driving circuit is provided, which includes a first signal generating module for generating the forward scan control signal based upon a first clock signal and a cascade signal; a control module for controlling an output of the cascade signal based upon the forward scan control signal and the reverse scan control signal; a latch module for latching the cascade signal by the first clock signal and the second clock signal; a processing module and a buffer module.
US10163406B2
This invention provides methods of and related apparatus for driving an electro-optic display having a plurality of pixels to display white text on a black background (“dark mode”) while reducing edge artifacts, ghosting and flashy updates. The present invention reduces the accumulation of edge artifacts by applying a special waveform transition to edge regions according to an algorithm along with methods to manage the DC imbalance introduced by the special transition. Edge artifact clearing may be achieved by identifying specific edge pixels to receive a special transition called an inverted top-off pulse (“iTop Pulse”) and, since the iTop Pulse is DC imbalanced, to subsequently discharge remnant voltage from the display. This invention further provides methods of and related apparatus for driving an electro-optic display having a plurality of pixels to display white text on a black background (“dark mode”) while reducing the appearance of ghosting due to edge artifacts and flashy updates by identifying specific edge pixels to receive a special transition called an inverted Full Pulse transition (“iFull Pulse”).
US10163404B2
The present image generator visually suppresses a gap between two adjacent reflective surfaces of a reflective display. The image generator comprises memory and a processor. The memory stores position of the gap on the reflective display. The processor analyzes a stream of images to be displayed on the reflective display and determines corresponding lighting data alongside the gap. The processor further controls at least one lighting unit located behind a seam inserted in the gap based on the determined lighting data.
US10163399B2
This disclosure relates to a DC-DC conversion control module, a DC-DC converter, and a display device. The DC-DC conversion control module includes a voltage input terminal, a control voltage output terminal, and a control sub-module; the control sub-module includes a delay unit, a switch unit, and an output control unit; the delay unit is configured to output a trigger signal after delaying for a time length; the switch unit is configured to, when receiving the trigger signal, make the path between the voltage input terminal and the input terminal of the output control unit be conducted; and the output control unit is configured to output a control voltage. Embodiments of the disclosure can realize adjustable delaying with respect to the output voltage of the DC-DC converter.
US10163390B2
Provided is a display control apparatus including: a display control unit configured to distribute brightness information to a plurality of display devices in accordance with external light amount information from a sensor; and a plurality of drive units configured to drive the plurality of display devices on a basis of the brightness information distributed by the display control unit.
US10163389B2
An electronic device includes an organic light emitting diode (OLED) display device, and a display controller configured to provide image data to the OLED display device. The display controller calculates stress data for the OLED display device by accumulating the image data, and determines a compensation factor for the OLED display device based on the stress data. The OLED display device receives the image data and the compensation factor from the display controller, converts the image data into compensated image data based on the compensation factor, and displays an image based on the compensated image data.
US10163384B2
A flat panel display includes: a substrate that includes a display region and a non-display region at a periphery of the display region; a pixel array disposed on the substrate of the display region; an input pad part disposed on the substrate of the non-display region; a bonding pad part disposed on the substrate of the non-display region, the bonding pad part including a plurality of output pads connected to the pixel array and a plurality of input pads connected to the input pad part; and a protective layer disposed on the substrate of the non-display region, the protective layer having openings formed therein that expose portions of the bonding pad part and the input pad part, wherein the opening of the protective layer is smaller than the bonding pad part, wherein the protective layer is thinner at a portion that overlaps the bonding pad part than at other portions.
US10163383B2
Disclosed is a display device that may include a GIP circuit, provided on a display area of a substrate, for supplying gate signals to gate lines, wherein the GIP circuit includes a thin film transistor provided in the boundaries between adjacent pixels.
US10163382B2
The liquid crystal drive apparatus drives a liquid crystal element. The apparatus includes an image data producer producing, using each of multiple input frame image data continuously input thereto, first frame image data and second frame image data, and a driver sequentially controlling, depending on the first frame image data and the second frame image data, application of a first voltage or a second voltage lower than the first voltage to each of multiple pixels of the liquid crystal element in respective multiple sub-frame periods included in one frame period to cause that pixel to form a tone. Pixel data at pixel positions corresponding to each other in the first and second frame image data have mutually different tones. A tone difference between the mutually different tones is 20% or less of a higher one of the mutually different tones.
US10163378B1
A multi-panel display project board with a center panel between two side panels and with a header panel movable between a fold-in position and a fold-out position. Each panel has a medium sandwiched between two linerboards. Creases between the panels are formed by slitting linerboard beneath the creases or by forming the creases each as a crushed score. The header panel has a long segment separated from two shorter segments by segment creases. When the header panel is in the fold-in position after pivoting from a fully folded orientation about panel creases, the shorter segments define respective obtuse angles with the long segment. In the fold-out position after pivoting the header panel about additional creases, the shorter segments define respective reflex angles instead. There is no footer or braces.
US10163376B2
There is provided a display assembly. The assembly includes an elongate mounting member. The mounting member has a top, a bottom spaced-apart from the top, and a plurality of spaced-apart grooves extending from the top to the bottom thereof. The assembly includes a plurality of planar members. Each of the planar member includes image indicia thereon. The planar members are shaped to fit within respective ones of the grooves, whereby the image indicia so arranged conveys a three-dimensional effect.
US10163370B2
A decoding apparatus performs self-correcting processing with a decoding capability providing apparatus holding a decoding key for decoding first ciphertext which can be decoded by homomorphic operation to obtain a decoding value of the first ciphertext, and performs non-homomorphic operation using a value corresponding to or deriving from the decoding value of the first ciphertext and an addition value to output plaintext.
US10163361B2
A method includes acquiring individual assessment data that includes behavior from player of a construction toy. The construction toy includes at least one sensor to detect an activity of the player with the construction toy. The method further includes determining a goal for the player based on the individual assessment data and a set of group assessment data. The method also includes providing a teaching based on the goal. The method includes permitting the player to play with the construction toy with reduced monitoring or intervention by the processing device during a free play period. The method further includes in response to a determination that free play period is over, prompting the player to perform an activity based on the goal. The method also includes in response to a determination that the player has completed the activity, providing a first reinforcement message to the player.
US10163360B2
A virtual-reality navigation controller includes a base and a seating portion. The seating portion includes a seat for supporting a weight of a user seated thereon, and a back-rest coupled to the seat to move integrally with the seat and to support the user's back. The virtual-reality navigation controller further includes a displacement connector between the seating portion and the base to reciprocate the seating portion upwards and downwards, and a motion-detection controller to measure upwards and downwards displacement of the seating portion. The displacement connector is configured to move the seating portion upwards along with the user to support the user when the user ascends from the seat during virtual-reality activities. The displacement connector is further configured to move the seating portion downwards at a slower maximum speed than the upwards movement, when the user's body rests back on the seat.
US10163349B1
The present disclosure relates generally to safety lighting devices for automotive vehicles. A safety lighting system coupled to an automotive vehicle includes a power source that is independent of an electrical system of the vehicle. The system also includes a lighting feature electrically coupled to the power source, wherein the lighting feature is configured to activate in response to an impact event.
US10163346B2
A computer system, method, and computer program product, for detecting a stay of a vehicle. The computer system includes an interface component configured to periodically receive location data sets (211-1 to 211-n) from one or more location sensors attached to the vehicle. The system further includes a motion detection component configured to detect a stop of the vehicle when at least two consecutive location data sets (211-1, 211-2) represent the same physical location within a tolerance range to define a stop location of the vehicle.
US10163341B2
The present disclosure relates to a stereoscopic sensor comprising: a first camera pair for capturing a first and a second image wherein the stereoscopic sensor is adapted to monitor and define a main surveillance zone in a surveillance plane at a predetermined distance from the stereoscopic sensor, said main surveillance zone comprising a first and a second surveillance zone and the first camera pair defines a first surveillance zone with a primary coverage in a first direction and a secondary coverage in a second direction wherein the stereoscopic sensor further comprises a second camera pair for capturing a first and a second image, said images being processable into a height image.
US10163340B2
The disclosure relates to a method (50) performed in a network node (3, 4, 5) for notifying a driver of a vehicle (7) about his or her driving. The method (50) comprises receiving (51) vehicle related information from a communication device (6) capable of receiving data from a data collector (8) of the vehicle (7); processing (52) the vehicle related information such as to establish a driving indicator of a driver of the vehicle (7) in relation to one or more other drivers; and transmitting (53) to the communication device (6) data indicating the driving indicator of the driver of the vehicle (7) in relation to other drivers. The disclosure also relates to a corresponding network node, computer program and computer program products. The disclosure further relates to a method in a communication device.
US10163338B2
A detection and transmission system includes a first detection and transmission device and a second detection and transmission device. The second detection and transmission device is disposed in a first direction from the first detection and transmission device. The first detection and transmission device generates a first sound signal toward the first direction when detecting a first moving object. The second detection and transmission device generates a second sound signal when receiving the first sound signal.
US10163324B2
A remote battery monitor that is configurable based upon the data from the battery and is able to monitor the condition of the battery while the battery is present in a circuit.
US10163323B1
A swimming pool safety surveillance system includes a camera identifying module, a terminal controller, and a camera identification monitoring module. The camera identifying module identifies the face of swimmers to generate a face information. The camera identification monitoring module tracks the face information around the facility environment of the swimming pool area, so as to produce a warning signal when the swimmer with corresponding face information is in an accident event, such that the emergency signal is sent to the terminal controller for sending a rescue warning. By intelligently tracking the face of swimmers, the swimming pool environment is under safety surveillance, whereby the rescue operation is immediately carried out for accident occurrence, and the swimming pool safety and the rescue efficiency are improved.
US10163322B2
A system comprises a patient bed having a reader to read wireless signals. In some embodiments a wound dressing has a transmitter that transmits wireless signals to the reader of the patient bed. In other embodiments, a garment has a transmitter that transmits wireless signals to the reader of the patient bed. In still further embodiments, other medical equipment has a transmitter that transmits wireless signals to the reader of the patient bed.
US10163319B2
A mobile tracking unit includes a controller having a processor, a memory in electronic communication with the processor, and instructions stored in the memory. The instructions are executable by the processor to communicate with a control unit of an automation and security system, determine a position of the mobile tracking unit relative to a base station using a low power location module, and communicate the position of the mobile tracking unit to at least one of the base station and a control unit of the automation and security system. When the mobile tracking unit is outside a specified range from the mobile tracking unit, the controller continues tracking the position of the mobile tracking unit with the low power location module. When the mobile tracking unit is inside the specified range, the controller determines the position of the mobile tracking unit using a high power location module.
US10163318B2
A system for detecting placement or misplacement of an object, comprising: a wireless tag; a first set of instructions which cause a first electronic device (“FED”) associated with the tag to automatically detect signals from the tag, determine a position of the FED, transmit the position and status to an external electronic device (“EED”) in response to the status indicating that the tag and the FED are within a predetermined range, and transmit the position and status to the EED in response to the status indicating that the tag and the FED are outside of the predetermined range; a second set of instructions which cause a second electronic device (“SED”) that is unassociated with the tag to automatically detect signals from the tag, determine a position of the SED, determine an identifier for the tag using the signals, and transmit the position and the identifier to the EED.
US10163297B1
Various embodiments of a gaming system and method are disclosed as having increased efficiency in game evaluations. The gaming system may incrementally evaluate a predetermined quantity of symbol sets for winning symbol combinations rather than evaluating all or substantially of the predetermined quantity of symbol sets at substantially the same time. The gaming system may also incrementally reveal the predetermined quantity of symbol sets to increase player anticipation of increased winnings.
US10163292B1
The present invention provides a vending machine monitoring system that includes a first mobile phone housed inside the vending machine. The system also includes an adapter device which is configured to be installed or retro-fitted in a vending machine. The adapter device is communicably coupled with a controller of the vending machine to monitor and control the various operations of the vending machine. In particular, the adapter device acts a bridge between the various cables, which carries signals related to the operations of the vending machine, and the controller. Further, the first mobile device is installed in the vending machine which is in wireless or wired communication with the adapter device, and allows the vending machine to accept contactless payments and record the inventory levels and payment information. The adapter device, along with the computing device, provides additional functionality of remotely monitoring and controlling the vending machine.
US10163287B2
A multi sensor detection and disabling lock system includes detector cases for holding interchangeable detectors that sample for chemical, biological and radiological compounds, agents and elements, with each detector case disposed in or upon the monitored product. The detector case transmits detection information to a monitoring computer terminal and transmits a signal to a lock disabler engaged to the product to lock or disable the product's lock thereby preventing untrained, unauthorized and unequipped individuals from gaining access and entry to the product, and also preventing further contamination of the area. The detection system can be interconnected to surveillance towers scanning detector cases disposed at seaport docks, freight depots and rail terminals for monitoring containers being prepared for shipment or sitting on docks for long periods of time.
US10163284B2
A method and system include monitoring to detect a crossing of a first geographic boundary and monitoring to detect a crossing of a second geographic boundary. When a crossing of the first geographic boundary and a crossing of the second geographic boundary are detected in succession, a first barrier system response is initiated. In some examples, when a crossing of the third geographic boundary and a crossing of the second geographic boundary are detected in succession, a second barrier system response is initiated.
US10163278B2
Methods and systems are provided for a vehicle wirelessly communicating with a central server. In one example, a method may include monitoring faults and sending engine conditions along with driver inputs to the central server for processing.
US10163267B2
Various embodiments provide methods and systems for users and business owners to share content and/or links to visual elements of a place at a physical location, and, in response to a user device pointing at a tagged place, causing the content and/or links to the visual elements of the place to be presented on the user device. In some embodiments, content and links are tied to specific objects at a place based at least in part upon one of Global Positioning System (GPS) locations, Inertial Measurement Unit (IMU) orientations, compass data, or one or more visual matching algorithms. Once the content and links are attached to the specific objects of the place, they can be discovered by a user with a portable device pointing at the specific objects in the real world.
US10163263B2
The technology uses image content to facilitate navigation in panoramic image data. Aspects include providing a first image including a plurality of avatars, in which each avatar corresponds to an object within the first image, and determining an orientation of at least one of the plurality of avatars to a point of interest within the first image. A viewport is determined for a first avatar in accordance with the orientation thereof relative to the point of interest, which is included within the first avatar's viewport. In response to received user input, a second image is selected that includes at least a second avatar and the point of interest from the first image. A viewport of the second avatar in the second image is determined and the second image is oriented to align the second avatar's viewpoint with the point of interest to provide navigation between the first and second images.
US10163250B2
Techniques for generating an arbitrary view from a plurality of other existing views are disclosed. In some embodiments, arbitrary view generation includes storing a set of images comprising a plurality of perspectives of an asset in a database and generating an image comprising a desired arbitrary perspective of the asset that is different than any of the plurality of perspectives by combining pixels comprising at least a subset of the set of images.
US10163247B2
A computing system is configured for context-adaptive allocation of render model resources that may sacrifice some level of detail in a computational description of a 3D scene before rendering in order to accommodate resource limitations in a rendering environment such as available processor cycles, and/or bandwidth for data transmission to a processor. Such resource limitations can often preclude rendering a richly detailed 3D scene, particularly in full-motion and/or in real time. An importance function describing the relative perceptual importance of elements that make up the 3D scene is utilized to enable resources to be adaptively allocated so that more resources go to visual elements of the 3D scene that have a higher perceptual importance. The rendered output may thus optimize visual fidelity for the computational description within the resource constrained rendering environment.
US10163245B2
Animations are displayed on a user interface (UI) of a computing device using one of multiple different animation system modes, each animation system mode operating in a different manner to determine how to change the display for an animation. The animation can be on a particular object that is displayed by the computing device (e.g., scrolling a list, moving an icon or character from one location to another) and/or can be on the display as a whole (e.g., panning or scrolling a view of the whole display). The multi-mode animation system operates to select an animation system mode on a frame by frame basis. For each frame of content being displayed on the display device, the multi-mode animation system selects an appropriate one of the animation system modes to use for generating the content of that frame.
US10163244B2
Methods and systems for creating animation elements from digital drawings. In particular, one or more embodiments detect a digital drawing input stream including a plurality of strokes. One or more embodiments identify a plurality of stroke points for each stroke from the plurality of strokes, and determine a plurality of timestamps for the plurality of stroke points. One or more embodiments generate an animation element based on the plurality of stroke points and the plurality of timestamps. One or more embodiments also receive a selection to insert the animation element into a user interface, and insert the animation element with associated drawing time information and stroke point information into the user interface in response to the received selection.
US10163239B2
A computer-aided diagnostic (CAD) apparatus and a CAD method based on the diagnostic intention of a user are provided. The CAD apparatus includes a region of interest (ROI) detector configured to detect an ROI from an image input from a probe, and a probe motion determiner configured to determine a motion of the probe in response to the ROI detector detecting the ROI. The CAD apparatus further includes a diagnostic intention determiner configured to determine a diagnostic intention of a user based on the determined motion of the probe, and a diagnostic intention processor configured to perform a diagnostic procedure based on the determined diagnostic intention of the user.
US10163231B2
A magnetic resonance (MR) imaging apparatus of embodiments includes processing circuitry. The processing circuitry generates a third k-space data group including a first k-space data group and a second k-space data group, by adding the second k-space data group that is arranged in a second range adjacent to a first range, to the first k-space data group that is arranged in the first range and that is undersampled along at least one of the axes in k-space as well as in any axis that is different from the axes in the k-space. The processing circuitry generates an MR image group by performing a reconstruction process on the third k-space data group.
US10163228B2
Provided is a medical imaging apparatus including: an image processor configured to extract properties that an object has with respect to at least one feature, based on a plurality of medical images of the object; and a controller configured to control a display to display a first medical image from among the plurality of medical images and the extracted properties and display a first property shown in the first medical image from among the properties and a second property not shown in the first medical image in such a manner that the first property and the second property are distinguished from each other.
US10163219B2
A cargo position tracking routine implemented in an electronic control unit of an automotive vehicle uses machine vision to monitor the position of cargo in a cargo area of an automotive vehicle and determine whether the cargo has shifted. Upon determining that the cargo has shifted, the cargo position tracking routine causes a driver of the vehicle to be alerted.
US10163210B2
An image sensor includes a substrate and a plurality of image sensor pixel arrays configured to obtain images having different characteristics. The plurality of image sensor pixel arrays are disposed in a row and spaced apart from one another by a predetermined distance on one surface of the substrate.
US10163196B2
An image processing device includes: an HDR image generating unit configured to generate an HDR image signal by first high dynamic range combining of a first signal including first image data and a second signal including second image data; a tone compressing unit configured to generate a first tone-compressed image signal to be displayed by performing tone compression processing on the HDR image signal generated by the HDR image generating unit; and a color correcting unit configured to generate a second tone-compressed image signal by second high dynamic range combining of at least the first and second signals based on the first tone-compressed image signal.
US10163192B2
This invention enables compression-coding of image data of a Bayer arrangement more efficiently. For this purpose, an encoding apparatus includes a generation unit which generates, from G0 and G1 component data of the image data of the Bayer arrangement, a GL plane formed from low-frequency component data of a G component and a GH plane formed from high-frequency component data of the G component, a luminance/color difference transforming unit which generates, from R and B component data of the image data of the Bayer arrangement and the GL plane, a luminance plane, a first color difference plane, and a second color difference plane, and an encoding unit which encodes the luminance plane, the first color difference plane, the second color difference plane, and the GH plane.
US10163188B2
A buffer write method for a buffer, including a plurality of M-bit storage units, has following steps: obtaining pixel data of a plurality of first N-bit pixels of a picture; calculating a corresponding start address of the buffer for the pixel data of the first N-bit pixels; and storing the first N-bit pixels of the picture according to the calculated start address of the buffer in the M-bit storage units by a buffer controller. The storing step includes fully storing at least one of the first N-bit pixels in one of the M-bit storage units storage units, wherein M and N are positive integers, and M is not divisible by N.
US10163186B2
The invention notably relates to a computer-implemented method for modifying a number of graphic cards used for rendering a scene, a graphic card comprising one or more graphic processing units. The method comprises providing a scene that is already loaded in a render engine, the scene comprising at least one graphic data to be used for rendering a view of the scene; modifying an abstract graphic resource for a graphic resource of the at least one graphic data, the abstract graphic resource storing an identifier of the graphic resource for each graphic card, by adding a new identifier of the said graphic resource for each newly added graphic card; transferring, on each newly added graphic card, the said at least one graphic data already stored on one of the graphic cards.
US10163181B2
For effective joint evaluation of a medical image dataset on a first data processing device and at least one second data processing device that is connected to the first data processing device via a data transmission network, a first application is performed in the first data processing device, and a second application is performed in the second data processing device. Each of the applications has a respective graphical user interface having at least one segment for display of a view of the image dataset. An image processing pipeline is associated with each segment for deriving the view from the image dataset. Partially processed data of the image dataset is decoupled from the image processing pipeline of the segment of the first application, is transferred to the second application, and there is coupled to the image processing pipeline of the segment of the second application for preparing the view.
US10163172B2
A method for calculating lists of events in activity streams includes calculating a list of activity events for a user's activity stream based on weights assigned to implicit actions and explicit actions; and prioritizing the list of the activity events in the user's activity stream based on the weights.
US10163171B1
In various embodiments, a content provider may provide interactive content that is a part of a social networking service. One or more frames may be embedded within the interactive content, where the one or more frames may be provided by a payment application. The payment application may be configured to enable a user to view a list of friends; enable the user to select (i) a fund amount and (ii) a friend from the list of friends to transfer the fund amount from the user to the friend; and communicate, by bypassing the content provider, with a payment host to transfer the fund amount from the user to the friend without additional information about the friend.
US10163168B2
A system provides on a graphical user interface user-selectable options corresponding to a first type and a second type of enhanced coverage options, available for a covered property, each of the enhanced coverage options providing one or more improvements to a property covered under a property insurance policy, in accordance with universal design principles, in the event of an incurred loss to the covered property. Responsive to user selection of a type, alternating images including an image of a damaged property and an image of the damaged property after repair and an improvement in accordance with universal design principles corresponding to the selected type of enhanced coverage option, are displayed.
US10163165B1
An impact-resistant, photovoltaic (IRPV) window system is provided. The system may include an IRPV window coupled to a structure, a controller, and an insurance computing device. The IRPV window may include an impact resistant (IR) layer, a photovoltaic (PV) material that may generate an electrical output, and an electrode coupled to the PV material that may receive the electrical output. The IRPV window may permit a portion of visible light to pass through the IRPV window. The controller may monitor the electrical output and generate a solar profile of the structure based upon the electrical output. The insurance computing device may receive the solar profile and determine if an insurance policy associated with the structure is eligible for a policy adjustment and/or an insurance reward or discount offer.
US10163160B1
A method for identifying whether a house qualifies for homeowner's insurance is provided. The method includes receiving, by a computer system, from a user device, an indication of the house. The computer system is operated on behalf of an entity that issues homeowner's insurance, The user device is operated by a prospective purchaser of the house, and the indication is sufficient to identify the house. The method also includes retrieving, from a first database, characteristics linked with the house. The characteristics include one or more geohazard characteristics. The method further includes determining, whether the house qualifies for homeowner's insurance by the entity that issues homeowner's insurance using the characteristics linked with the house, storing, data indicating whether the house qualifies for homeowner's insurance, and transmitting to the user device of the prospective purchaser, the indication of whether the house qualifies for homeowner's insurance.
US10163147B2
A method for generating a list of recommended merchants based on an input merchant is provided. The method uses a recommender computing device. The method includes receiving an input merchant identifier, retrieving a first electronic data signal based on the input merchant identifier including historical transaction data of the input merchant including historical payment transactions initiated by candidate cardholders with the input merchant, and storing a list of the candidate cardholders. The method further includes retrieving a second electronic data signal that includes historical transaction data for at least some of the candidate cardholders included in the list of candidate cardholders and a candidate merchant identifier that identifies the candidate merchants, generating a list of candidate merchants from the second data signal including a ranking of the candidate merchants, and generating a list of recommended merchants based on the list of candidate merchants.
US10163144B1
Techniques for extracting unstructured quantitative data may be provided. For example, a process may attempt to extract unstructured quantitative data to form structured data. This quantitative data may be used for searchable ordering of items in an electronic marketplace. For example, a process may attempt to find common attributes amongst several item descriptions. The common attributes may be recognized in the unstructured data, stored as structured data, and incorporated with a network page to allow the user to search for a particular item with a particular attribute. The desired attribute can help narrow a set of results from a search query.
US10163139B2
A transport arrangement system operates to receive a transport request from a user, and to make a selection of a vehicle type for the user based at least in part on a set of criteria associated with the transport request or user information. For example, the determination of whether an autonomous vehicle is to be provided can be based at least in part on the destination specified with the transport request.
US10163131B2
In various example embodiments, systems and methods to provide proximity recommendations are provided. In example embodiments, data representing prioritized recommendations for a user is received. The data representing the prioritized recommendations is used to generated a composite visual representation by embedding select prioritized recommendations into a visual representation. The composite visual representation presents a higher prioritized recommendation in a more spatially prominent manner than a lower prioritized recommendation. The composite visual representation is then presented to the user.
US10163130B2
Methods and apparatus for identifying on-line users for advertisement or content targeting are disclosed. Historical user data is obtained in association with user identifiers, which have been unambiguously determined. The historical user data includes event data for one or more on-line user events that have occurred for each user identifier. The historical user data also specify fingerprint vectors of characteristic values that are each associated with specific ones of the user identifiers. A current one of the fingerprint vectors that is ambiguously associated with two or more user identifiers is received. A first user identifier is selected from the associated two or more user identifiers of the current fingerprint vector based on the event data of the historical user data. The selected first user identifier is provided to a server configured to provide advertisement or content based on user profile data that is obtainable for such selected first user identifier.
US10163128B2
A method to perform spatiotemporal events marketing includes: presenting, by a server, an interface on a display of a customer device, wherein the interface comprises a selectable list of times in which an event is to occur; determining, by the server, a route to the event or from the event, by a user of the customer device; and presenting, by the server, a selectable list of offers in the interface, wherein the list of offers is based on the selected time, a location of the event, and the route.
US10163120B2
Loyalty programs can be operated within a payment processing system having multiple vendors, thereby providing access to detailed transaction data and with the flexibility for customization of the loyalty programs themselves, by establishing a communication for the transfer of data via a customer-facing channel. When the payment processing system processes a transaction between a merchant and an account holder, in addition to obtaining payment for the merchant from the account via an acquirer and an issuer, respectively, a transaction handler tabulates and stores different types of loyalty currencies in a loyalty reward account associated with the account holder if the account holder is enrolled in a loyalty program and criteria for applying the loyalty program are satisfied. The account holder is provided access to the loyalty account via the customer-facing channel.
US10163108B1
Embodiments of the present invention provide systems and methods for generating policy-based transaction alerts. In accordance with the systems and methods, an alert generation engine transparently detects ongoing transactions without participating in the transaction path, and generates policy-based alerts.
US10163107B1
In some examples, methods and systems may institute technical fallback by determining, by a payment processing system, and based on analysis of the communication status indicator and the data obtained when a magnetic stripe of the payment object is introduced in magnetic stripe object reader, whether the payment object was swiped while an EMV object reader was communicatively coupled to the POS terminal. If the magnetic stripe of the payment object was swiped while the EMV object reader was connected to the POS terminal, the payment processing system extracts a transaction count indicating a number of times the customer has attempted to insert a chip of the payment object into the EMV object reader prior to swiping magstripe. By comparing the transaction count with a threshold count, the payment processing system authorizes the payment transaction as a technical fallback transaction if the transaction count is greater than the threshold count.
US10163090B1
A system and machine-implemented method for providing a user with a set of user-generated labels for tagging an item, the method including providing an item for display to a user, receiving an indication of a request from a user to tag the item, identifying a user-generated label set including a plurality of user-generated labels uniquely associated with the item, wherein a user-generated label is associated with an item in response to one or more of the user-generated label being previously used to tag the item or the user-generated label being pre-assigned to the item, each user-generated label of the plurality of user-generated labels representing a sentiment regarding the item and being associated with a fitness value, selecting one or more user-generated labels of the plurality of user-generated labels in response to receiving the indication and providing the one or more user-generated labels for display to the user.
US10163073B2
A method for organizing a message thread containing one or more messages. A root message and reply groupings are identified, each reply grouping depending from the root message. Each reply grouping has one or more child reply messages depending from a common parent message. The child reply messages within each reply grouping are ordered in chronological order based on the time of each of the one or more child reply messages was received or sent. The reply groupings are hierarchically ordering based on a relationship between the reply grouping and its parent message. A single display allows a user to view the message thread and the content of all of the messages in accordance with the hierarchical ordering.
US10163072B2
Disclosed embodiments provide systems and techniques for mass execution of analytical models across multiple dimensions of client, collateral, deal structure, third party, and other data relevant to predicting optimal decisions in real-time. In some embodiments, disclosed systems and techniques increase decisioning speed through the reduction of computational loads on disclosed decisioning systems. Further disclosed systems and techniques may scale-out analytical modeling computations through, among other technological solutions, advanced execution environments that are asynchronous and non-blocking in nature so as to allow the execution of a plurality of analytical models in parallel and optimizing the results.
US10163069B2
Proposed is an autonomous vehicle (AV) for delivering an item to a recipient at a delivery location in a trusted manner. The AV includes: a sensor system adapted to detect, while the autonomous vehicle is travelling to the delivery location, a value of a property of at least one of: the autonomous vehicle, and the item. The AV further includes a data store adapted to store authentication data for verifying the trustworthiness of the item, the authentication data being based on the value detected. The AV further includes a recipient verification unit adapted to verify the identity of the recipient and to generate a verification signal indicative of whether the identity of the recipient is verified. The AV further includes a communication unit adapted to communicate stored authentication data to an authentication system for verification.
US10163068B2
A pharmaceutical filling system for a high volume pharmacy is described. The system can include a manual pick/pack device and method. The system may include a rotation assembly, a left door and a right door, both positioned below the rotation assembly, a left divider positioned below the left door, and a right divider positioned below the right door, and a left gathering table positioned below the left divider, and a right gathering table positioned below the right divider. The system may also include a control device in electronic communication with the rotation assembly, the doors and the dividers for control of same.
US10163063B2
Computer program products and systems are provided for mining for sub-patterns within a text data set. The embodiments facilitate finding a set of N frequently occurring sub-patterns within the data set, extracting the N sub-patterns from the data set, and clustering the extracted sub-patterns into K groups, where each extracted sub-pattern is placed within the same group with other extracted sub-patterns based upon a distance value D that determines a degree of similarity between the sub-pattern and every other sub-pattern within the same group.
US10163057B2
A method, system and computer-usable medium for providing composite cognitive insights comprising receiving streams of data from a plurality of data sources; processing the streams of data from the plurality of data sources, the processing the streams of data from the plurality of data sources performing data enriching and generating a sub-graph for incorporation into a cognitive graph; processing the cognitive graph, the processing the cognitive graph providing a plurality of individual cognitive insights; generating a composite cognitive insight, the composite cognitive insight being composed of the plurality of individual cognitive insights; and, providing the composite cognitive insight to a user via a set of cognitive media content.
US10163049B2
A system and method for generating virtual objects, the data for the virtual object is retrieved at least in part from a tag. The tag comprises a transparent physical surface and a visually imperceptible structure constructed in the transparent physical surface. The tag encodes the data for the virtual objects in the visually imperceptible structure. When detected by the appropriately configured capture devices, the visually imperceptible structure produces a depth pattern that is reflected in phase shifts between regions in the tag.
US10163048B2
The present disclosure provides a page synchronization method. The method includes: acquiring and parsing a two-dimensional code to obtain to-be-synchronized page data contained in the two-dimensional code; identifying a page address and page progress information from the to-be-synchronized page data; generating an execution code for indicating the page progress according to the page progress information; loading a page according to the page address; and executing the execution code while loading the page, and displaying the page according to the page progress indicated in the execution code. The disclosed method can solve the problem in the prior art that the page progress cannot be automatically synchronized during page synchronization, and can thus improve the user experience.
US10163044B2
The present invention embraces methods to automatically adjust print locations on a label on center-tracked printers. The methods are applicable for the initial out of the box setup and when changing media/print scripts after deployment of the printer. A novelty of the present invention is that no additional hardware may be required and the method is implemented with a relatively simple software algorithm. By utilizing a simple software algorithm and an analysis of the objects (barcode, text, shape, graphics, etc.) in the rendered image buffer, the centered position for the label can be calculated. The calculation of the centered position for the label is based on the print head width and the image width. An additional benefit with this invention is that the risk of printing outside the physical label (due to mechanical or label media roll variations) is minimized, since the image is printed centered.
US10163034B2
Systems, methods, and other embodiments associated with tripoint arbitration for data classification are described. In one embodiment, a method includes receiving a query data point for classification, an arbiter point, a first set of classified data points belonging to a first class and a second set of classified data points belonging to a second class. A class-aggregated similarity metric for the query data point and each set is determined based, at least in part, on tripoint arbitration coefficients for data point pairs that include the query data point and a classified data point in the set, as calculated using the arbiter point. The query data point is classified based on a comparison of the similarity metric determined for the first set and the similarity metric determined for the second set.
US10163024B2
Provided are: an acquisition section that acquires image data; a detection section that detects a marker portion indicated in the image data; a communication section that performs communication with either one or a plurality of external servers including at least one of a plurality of dictionary functions; a processing section that (i) specifies, from the dictionary functions, a dictionary function in accordance with a type of the marker portion, and (ii) causes the communication section to transmit, to the external server including the specified dictionary function, an instruction to search for a text indicated by the marker portion, and for information related to the text, by using the dictionary function; and a generation section that generates a glossary including the received information related to the text upon reception of the information related to the text as a search result from the external server by the communication section.
US10163020B2
There is provided a system configured to receive a plurality of images, analyze a set of features of the plurality of images to determine a difference between a first training performance of a plurality of independent detectors based on one or more of individual attributes and a second training performance of a plurality of joint detectors based on one or more of composite attributes, select, based on the analyzing, either one of the plurality of independent detectors or one of the plurality of joint detectors for identifying a plurality of objects in the plurality of images, and identify the plurality of objects in the plurality of images, using the selected one of the plurality of independent detectors utilizing the one or more of the individual attributes or using the selected one of the plurality of joint detectors utilizing the one or more of the composite attributes.
US10163017B2
Systems and methods are provided for analyzing vehicle signal lights in order to operate an autonomous vehicle. A method includes receiving an image from a camera regarding a vehicle proximate to the autonomous vehicle. Data from a lidar sensor regarding the proximate vehicle is used to determine object information for identifying a subsection within the camera image. The identified subsection corresponds to an area of the proximate vehicle containing one or more vehicle signals. One or more vehicle signal lights of the proximate vehicle is located by using the identified camera image subsection as an area of focus.
US10163014B2
The disclosed embodiments include a method for monitoring the visual behavior of a person. In one embodiment, the method includes a person activity data providing step during which person activity data indicative of an activity of the person are provided; a person visual behavior data providing step during which person visual behavior data indicative of the visual behavior of the person related to said activity of the person are provided; reference visual behavior providing step during which a reference visual behavior data indicative of the reference visual behavior of the person based on said activity of the person are provided; and a comparing step during which the person visual behavior data and the reference visual behavior data are compared so as to deduce whether the person visual behavior is adapted with respect to said activity of the person.
US10163003B2
Certain embodiments involve recognizing combinations of body shape, pose, and clothing in three-dimensional input images. For example, synthetic training images are generated based on user inputs. These synthetic training images depict different training figures with respective combinations of a body pose, a body shape, and a clothing item. A machine learning algorithm is trained to recognize the pose-shape-clothing combinations in the synthetic training images and to generate feature descriptors describing the pose-shape-clothing combinations. The trained machine learning algorithm is outputted for use by an image manipulation application. In one example, an image manipulation application uses a feature descriptor, which is generated by the machine learning algorithm, to match an input figure in an input image to an example image based on a correspondence between a pose-shape-clothing combination of the input figure and a pose-shape-clothing combination of an example figure in the example image.
US10163002B2
A pedestrian detection system including a camera device and a cloud server. The cloud server includes an entrance node and a compute node unit including a plurality of compute nodes. The entrance node is configured to receive image data from the camera device, to divide the image data into a plurality of subordinate task areas, and to extract a percent of the subordinate task areas. The compute node unit is configured to receive the percent of the subordinate task areas from the entrance node, and processes simultaneously the percent of the subordinate task areas. Therefore, an efficiency of processing image of pedestrian can be improved.
US10163001B2
The virtual model control system has an input device configured to provide input information for formation, movement or transformation of a virtual model; a control device configured to form the virtual model based on the input information received from the input device, move or transform the virtual model, form a plurality of physical particles at the virtual model, form contact point information therefor, and move the plurality of physical particles to update the contact point information; an output device configured to output the virtual model to the outside. When the plurality of physical particles penetrates into another virtual model in the virtual space, the control devices update the contact point information so that the penetrating physical particles are rearranged at an outer side of the another virtual model.
US10163000B2
A method and corresponding apparatus include extracting a movement trajectory feature of an object from an input video. The method and corresponding apparatus also include coding the extracted movement trajectory feature, and determining a type of a movement of the object based on the coded movement trajectory feature.
US10162999B2
In one embodiment, a method includes accessing an image file associated with a first user of a communication system and detecting a face in an image corresponding to the image file. The method also includes accessing an event database associated with the communication system, the event database containing one or more events, each being associated with the first user and one or more second users of the communication system. The method also includes determining one or more candidates among the second users to be matched to the face, where each candidate is associated with an event in the communication system, and where a time associated with the image is in temporal proximity to a time associated with the event.
US10162990B2
Analog heterogeneous tags and methods and systems to configure the tags are described. The present invention relates to the field of electronic devices and more particularly to electronic tag devices using analog technology. Embodiments herein disclose a tag that can work in at least one of transmit only, receive only or transmit/receive modes and can transmit/receive using a plurality of communication technologies without the complex stack functionality with minimal hardware and memory requirements, wherein the tag uses I/Q samples corresponding to each technology pre-stored on the tag. Embodiments herein also disclose methods and systems for configuring the electronic tags using a configuration device, wherein the configuration device provides the I/Q samples of each technology to the tag.
US10162984B2
A method of destroying file contents of a file includes storing the file in a predefined file format, wherein a first part of the algorithm is integrated into a pre-execution header of the file called by an executing program or an executing operating system when the file is opened and a second part of the algorithm is integrated into a second part of the file, called by the first part of the algorithm when the first part of the algorithm is called by the executing program or the executing operating system, and modifying of the integrated algorithm includes modifying a storage structure of the algorithm so that it occurs in changed form after the opening of the file and cannot be recognized as before and storing the modified algorithm in the file.
US10162982B2
Implementations of the present disclosure include methods, systems, and computer-readable storage mediums for receiving, by an authorization manager of a cloud-platform, a request from an application, the request indicating a request to access personal user data stored in a database system of the cloud-platform, determining, by the authorization manager and based on user input from a user, that access to the personal user data is to be granted, and in response: providing, by the authorization manager, an access token to the application, receiving an access request from the application, the access request including the access token, and selectively providing the personal user data from a database container of the database system based on the access token, the database container being specific to the user.
US10162977B2
A data security system for securing the critical data of an on-board airplane avionics system comprising access control means for controlling access to the said data on the basis of the security related information of a user, wherein the security related information is selected from the group consisting of: a list of authorised users; a maximum number of allowed accesses, as well as the types of allowed accesses; a time window allowed for access; a series/concatenation allowed for access, by various different users; and a hierarchical prioritisation of the zones associated with the data storage means.
US10162976B2
Systems and methods for detecting potential steganography use to hide content in computer files transmitted via electronic communications are provided. An electronic communication associated with a computer file may be identified. The communication and the computer file may be analyzed to determine whether the computer file potentially includes hidden content. To determine whether the computer file potentially includes hidden content, a set of steganographic criteria may be analyzed. If at least a portion of the steganographic criteria are satisfied, then it may be determined that the computer file potentially includes hidden content. If at least a portion of the steganographic criteria are not satisfied, then it may be determined that the computer file does not potentially include hidden content. If the computer file is determined to potentially include hidden content, an individual may be notified of the communication associated with the computer file.
US10162971B2
In some embodiments, a first device may generate a data block for an ordered set of data blocks such that the data block is cryptographically chained to a given data block preceding the data block in the ordered set. The first device may obtain an encryption key used to encrypt information related to the data block, and use group members' keys to encrypt the encryption key to generate a group key. As an example, the group's members may include a first member associated with the first device and other members. The keys used to encrypt the encryption key may include the other members' keys. The first device may transmit the ordered set and the group key to a communication resource (e.g., accessible by the members). Other devices (associated with the other members) may use the ordered set and the group key to obtain content related to the ordered set.
US10162967B1
A system for evaluating a target file includes an endpoint computer that receives similarity digests of legitimate files, receives a target file, and generates a similarity digest of the target file. The endpoint computer determines whether or not the target file is legitimate based on a comparison of the similarity digest of the target file against the similarity digests of the legitimate files. The system further includes a backend computer system that receives the legitimate files, generates the similarity digests of the legitimate files, and provides the similarity digests of the legitimate files to the endpoint computer.
US10162963B2
A method is provided for detecting malware, such as a virus or spyware. The method looks for deviations expected operating parameters instead of focusing solely on conventional malware signatures. The method includes monitoring current operating parameters for a computing system running one or more application, obtaining baseline operating parameters for the computing system running the one or more application in the absence of malware, identifying a deviation between the current operating parameters and the baseline operating parameters, and determining whether the identified deviation matches a deviation associated with a predetermined malware definition.
US10162961B1
The disclosed embodiments include systems and methods for managing an authentication credential of an account of a machine of a computer system via a remote connection with the machine. A method includes accessing in the computer system, at least one credential parameter for an authentication process for the account of the machine, the at least one credential parameter being included in an authentication file associated with the computer system. The method also includes determining a password complexity rule for the account based at least on the at least one accessed credential parameter, thereby enabling automatic generation of a password consistent with the determined password complexity rule for a user associated with the account of the machine, and determining a credential management protocol, based on interaction with the machine via the remote network connection, thereby enabling updating a password for the account at the machine based on the automatically generated password.
US10162957B2
An authentication method includes sending out a first authentication request; receiving first authentication information of a first authentication item; determining whether the first authentication information is correct; determining whether a first weighting value is equal to or is larger than a threshold value; sending out a second authentication request when the first authentication information is correct and the first weighting value is smaller than the threshold value; receiving second authentication information of a second authentication item; determining whether the second authentication information is correct; determining whether a first sum value of the first weighting value and a second weighting value is equal to or is larger than the threshold value; and permitting a web system to be logged in when the second authentication information is correct and the first sum value is equal to or is larger than the threshold value.
US10162952B2
Systems and methods for providing information security in a network environment are disclosed. The method includes initiating processing, invoked by a user, of at least one of a plurality of objects in a processing unit of a hardware layer, wherein the plurality of objects is hosted for a tenant. The method further includes determining that the processing of the at least one of the plurality of objects by the processing unit is authorized by the tenant based on a security map provided by the tenant and accessible by the processing unit within the hardware layer. The method further includes allowing the processing of the object based on a result of the determining.
US10162948B2
An authentication system in accordance with an example includes an image capture device to scan an object. The authentication system also includes an authentication module to identify imperfections in the object based on the scan, to generate model data based on the identified imperfections, and to authenticate the user based on a comparison of currently identified imperfections to the model data.
US10162938B2
A health management system. A method of operating a home gateway for a home network connectable with at least one home device in the health management system includes receiving health information for at least one user from a health management server, generating environment control information for configuring an environment corresponding to the health information for the at least one user, and transmitting the environment control information to the at least one home device to control the at least one home device.
US10162922B2
A computer-implemented method for generating a circuit design is provided according to certain aspects. The method includes determining a gating efficiency of first gate-enable logic, determining a gating efficiency of second gate-enable logic, and determining one of the first gate-enable logic and the second gate-enable logic having a greater one of the determined gating efficiencies. The method also includes placing the determined one of the first gate-enable logic and the second gate-enable logic in clock gating logic of the circuit design, and placing another one of the first gate-enable logic and the second gate-enable in data gating logic of the circuit design.
US10162921B2
The following description is directed to a logic repository service. In one example, a method of a logic repository service can include receiving a first request to generate configuration data for configurable hardware using a specification for application logic of the configurable hardware. The method can include generating the configuration data for the configurable hardware. The configuration data can include data for implementing the application logic. The method can include receiving a second request to download the configuration data to a host server computer comprising the configurable hardware. The method can include transmitting the configuration data to the host server computer in response to the second request so that the configurable hardware is configured with the host logic and the application logic.
US10162920B1
The present disclosure relates to systems and methods for performing out of order name resolution in an electronic design language. Embodiments may include receiving, one or more design units associated with an electronic design and registering the one or more design units in a registry database. Embodiments may further include performing local name resolution for each element reference within at least one of the one or more design units. In response to registering, embodiments include identifying at least one element reference upon which local name resolution was not performed and obtaining an appropriate element reference from the registry database. Embodiments may further include reviewing at least one secondary design unit for one or more local declarations and performing local name resolution for one or more remaining element references using a design hierarchy.
US10162919B1
A method for designing a system on a target device includes identifying an exclusive-OR (XOR) network in a design for the system that matches an XOR network in a library. The XOR network in the design is replaced with a preferred XOR network in the library.
US10162914B1
A method and apparatus for forcing equivalent outputs at start-up for replicated sequential circuits is disclosed. An integrated circuit (IC) includes first and second clocked logic circuits each coupled to receive a clock signal common to both, and each configured to produce equivalent logical outputs based on a common set of logic inputs. The IC further includes an equivalence circuit coupled to the outputs of each of the first and second clocked logic circuits. During a system start-up (e.g., power on) and before the clock signal has been applied, the equivalence circuit may detect if the outputs of the to first and second clocked logic circuits originally come up in different states. Responsive to determining that the outputs of the first and second clocked logic circuits are different, the equivalence circuit may cause the outputs to be forced to the same logical state.
US10162911B2
Downhole drilling tools designed and manufactured to minimize or reduce imbalance forces and wear by disposing cutting elements in cutter groups and cutter sets in a level of force balance and by placing impact and/or wear resistant cutters on blades subject to high impact forces and/or large loadings. Manufacturing costs may be reduced by placing inexpensive cutters on blades not subject to high impact forces and/or loadings. Some embodiments comprise designing downhole tools with combinations of thicker blades to receive high impact forces and/or loadings with thinner blades. Some embodiments comprise designing downhole drilling tools with optimized fluid-flow properties. Designing methods may comprise performing simulations on a designed tool, evaluating respective forces acting on cutters during simulated engagement with a downhole (uniform and transitional) and/or evaluating wear on cutters and bit, and/or CFD simulations to evaluate fluid-flow optimization on a tool. Various cutter layout procedures and algorithms are described.
US10162910B2
A method and apparatus for determining settings of wires in an electrical system are provided. The method includes setting a first wire setting of a wire from among a plurality of wires to a pin setting of a pin attached to the wire if the pin has a pin setting; setting the first wire setting to a first connector setting of a first connector attached to the pin if the pin does not have a pin setting and the connector setting includes a default setting; and setting the first wire setting to at least one from among: a second pin setting of a second pin attached to the wire from among the plurality of pins; and a second connector setting of a second connector attached to the second pin if the pin does not have a pin setting and the first connector setting does not have a default setting.
US10162897B2
A knowledge sharing system includes a social network service (SNS) providing server that stores relationship information between a first user and a second user. The knowledge sharing system includes a knowledge sharing service providing server including a query data management unit that stores query data when the query data is transmitted from a first terminal of the first user and stores a query sharing request in association with the query data when the query sharing request is transmitted from a second terminal of the second user, and in the storing of the query sharing request, the query data management unit matches the query sharing request with the query data; and a query data providing unit that provides the query data matched with the query sharing request to a third terminal of a third user, where the third user is connected with the second user in the SNS platform.
US10162894B2
Social network content consumption activities of social network users related to content published by at least one social network are monitored. The monitored social network content consumption activities of each of at least two of the social network users are compared. A determination is made, based upon the comparison, that a difference in consumption of the published content exists between the at least two of the social network users. A notification is generated to any of the at least two of the social network users determined, based upon the difference in consumption, to have consumed less of the published content than at least one other social network user.
US10162881B2
Embodiments are directed towards managing data. Attributes of model fields of a plurality of model objects may be analyzed. If the analysis of the attributes discovers primary key fields in the model objects, the characteristics of the primary keys may be compared with the characteristics of other model objects. If affirmative results of the comparison indicate that one or more foreign key fields may be in the other model objects, one or more relationships that associate the primary key fields with the foreign key fields may be provided. And, a system model may be provided based on the relationships and the model objects that include the primary key fields and the model objects that include the foreign key fields.
US10162878B2
An information handling system performs a method for finding a nearest neighbor of a point. In some embodiments, the method may be used for agglomerative clustering. The method includes projecting a space Θ of a first dimension with a first distance μ to a space P of a second, smaller dimension with a distance μ′ by a projection function p. For all pairs of points v1 and v2 in Θ, μ′ (p(v1), p(v2))≤μ(v1, v2), where p is the function that projects points in Θ to points in P. The method also includes selecting a point v in Θ and performing a search for its nearest neighbor in Θ by projecting v to P and locating a set S of nearest neighbors in P of p(v). A search is then performed in Θ of a set of S′ of points that project onto the points in S.
US10162877B1
Implementations described and claimed herein provide systems and methods for automatically compiling content for a particular project. In one implementation, a compilation template for the particular project is retrieved. The compilation template has instructions for compiling a plurality of content files. The compilation instructions include a designation for each of the content files including a path to a source of the content file and a target file type. Each of the content files is retrieved from the source, and each of the retrieved content files has a source file type. Each of the retrieved content files is modified from the source file type to the target file type. The modified content files are compiled into a content set based on the compilation instructions. A framework is generated to display the compiled content set. An archive file storing the generated framework for displaying the compiled content set is output.
US10162872B2
In accordance with embodiments, there are provided mechanisms and methods for performing a synchronization of data. These mechanisms and methods for performing a synchronization of data can enable a more efficient synchronization, time and resource savings, an enhanced user experience, etc.
US10162868B1
Data mining systems and methods are disclosed for evaluating pairwise substitutability relationships among items. For example, a pairwise similarity measure may correspond to a value quantifying the extent to which an item A is favored over an item B by a population of users. Given a base item selected by a user, the system may select a candidate item from a set of potential substitute items for the base item based on current estimates of corresponding pairwise similarities. The system may then present the candidate item to the user in a context of comparison against the base item and obtain an indication of user preference between the two. The system may then update corresponding pairwise similarities based on the indication of preference.
US10162856B1
The present invention extends to methods, systems, and computing system program products for incrementally calculating correlation for Big Data or streamed data. Embodiments of the invention include incrementally calculating one or more components of a correlation for two modified computation subsets based on one or more components calculated for two previous computation subsets and then calculating the correlation based on the incrementally calculated components. Incrementally calculating the components of a correlation avoids visiting all pairs of data elements in the two modified computation subsets and performing redundant computations thereby increasing calculation efficiency, saving computing resources and reducing computing system's power consumption.
US10162848B2
In some embodiments, a data harmonization system can organize, classify, analyze and thus relate previously unrelated data stored in multiple databases and/or associated with different organizations. In such embodiments, the data harmonization system can relate such previously unrelated data sets to, for example, track trends, exceptions, inconsistencies, location, etc. such that determinations can be made based on such different and/or previously unrelated data sets. In such embodiments, the data harmonization system can be used to harmonize both structured data and/or unstructured data based on concept-based analysis.
US10162844B1
A system for using conversational similarity for dimension reduction in deep analytics, comprising a self-learning interaction optimizer that receives string-based data from a contact center and analyzes it to produce a plurality of information similarity vectors, provides the vectors to a neural network and receives output vectors from the neural network, and produces context data from the output vectors and associates the context data with the original string-based data.
US10162843B1
A computer-executable method, computer program product and system for managing metadata in a distributed data storage system, wherein the distributed data storage system includes a first node and one or more data storage arrays, the computer-executable method, computer program product and system comprising partitioning management of metadata created in the distributed data storage system into one or more portions of metadata, wherein the first node manages a first portion of the one or more portions of metadata, and storing the metadata using the first node.
US10162842B2
Apparatuses, methods and storage medium associated with processing data are disclosed herewith. In embodiments, an apparatus may include a data pre-processor to partition a collection of scalar data associated with unidirectional relationships of a plurality of two endpoint pairs into a plurality of workloads of directional data associated with the plurality of two endpoint pairs. In embodiment, the partition operation may include partition of the two endpoint pairs into a plurality of bins, where each bin includes a plurality of quantiles of the two endpoint pairs. Other embodiments may be described and/or claimed.
US10162840B1
According to an embodiment of the present invention, a system and method for consolidating financial data comprising: a relational database containing a plurality of schema comprising a staging schema, recent schema and historic schema; a distributed data storage platform comprising a plurality of nodes; and a computer processor, coupled to the relational database and the distributed data storage platform, and programmed to: store financial data in the distributed data storage platform comprising the plurality of nodes; create an aggregation specification to compute an aggregation for a financial measure; determine whether the aggregation is current; compose one or more keys for the aggregation specification; determine one or more dimensions for the keys; responsive to the keys and dimensions, process the aggregation specification via the plurality of nodes; and combine one or more aggregations to create a new aggregation algorithm.
US10162832B1
Approaches for reducing a storage footprint for one or more files. A file type associated with a digital file is determined. A deduplication process is performed on the digital file based, at least in part, on the determined file type. The deduplication process may be performed differently on the digital file based on whether the digital file is an image or audio file, a compressed file, or a columnar file, for example. By considering the type of file being deduplicated, enhanced reductions in the storage footprint of the digital file may be realized.
US10162807B2
A technique is provided for editing an attachment included in an email message. The attachment is displayed within a message body of the email message and can be edited directly within the message body. Specifically, the technique involves launching a markup application that generates an editable version of the attachment within the message body. The markup application allows a user to make edits to the editable version of the attachment without leaving the email message.
US10162806B1
The subject matter of this specification can be embodied in, among other things, a method that includes receiving an indication that a first activity has occurred. The first activity is associated with a uniform resource identifier (URI) that specifies at least one web page. The method also includes identifying an application that is associated with the URI using a registry that associates particular URIs with particular applications, retrieving, using the identified application, content associated with the URI, displaying the content or information derived from the content in a first format that is not controlled by a second format specified by a markup language of the at least one web page.
US10162797B1
A computing device is described that is configured to display a graphic visualization representing a physical work site for conveying whether a member is accessible as a function of parameters. In an implementation, the computing device includes a display device, a memory, and a processor communicatively coupled to the memory and the display device. The computing device includes a module stored in memory and executable by the processor. The module is configured to instruct the processor to receive parameters. The module is configured to cause the processor to determine liftability of at least one member. The module is configured to cause display of a graphic visualization representing a physical work site at the display device. The graphic visualization includes a graphical representation of the member. The graphical representation is displayed in a first hue when the crane can lift the member.
US10162788B2
A multi-host endpoint reflector enables a method of communication between multiple USB hosts through the USB devices connected to them, where data from one USB host is routed across the USB devices between endpoints of complimentary directions to one or more additional USB hosts. The multi-host endpoint reflector may be integrated with a USB hub controller to form a USB compound device to create a multi-host endpoint reflector hub. A USB multi-host endpoint reflector hub enables a USB OTG B device to become a host upon request by providing a data bridge between the OTG B device after it has transitioned to a host role while any other OTG A device that already is a host is not required to change its host role to a slave role. Therefore a plurality of OTG host devices may co-exist on the same interconnection system hub and communicate there between.
US10162787B1
A system and related method for PCIe device configuration in a certified multi-core avionics processing system on which several guest operating systems (GOS) are running may allow a GOS to access or communicate with PCIe devices not owned by that GOS. The system may configure PCIe controllers and the PCI devices connected by those controllers by issuing addresses and determine, via a configuration vector of the system hypervisor, which PCIe devices are accessible to which non-owning guest operating systems. The hypervisor may provide each non-owning GOS with the GOS physical addresses corresponding to each non-owned PCIe device accessible to that GOS. Configuration of an unpowered or otherwise unprepared PCIe device may be deferred until device information is requested by the owning GOS to preserve compliance with system timing requirements.
US10162786B2
A storage node includes a storage element module. The module includes a first peripheral component interconnect express (PCIe) switch suitable for uplink connection, a second PCIe switch coupled to the first PCIe switch, and at least one connection element coupled to the second PCIe switch, suitable for coupling with at least one storage element. All PCIe end point elements and uplink connection elements are in a PCIe card form factor as defined in PCI Express Card Electromechanical Specification.
US10162776B2
A method for maintaining data and clock line synchronization, which may include a clock line that may be driven high after a clock line falling edge to mitigate a clock error. Additionally, the clock error may be mitigated by maintaining a saturated state of a device. Furthermore, a register may be connected to a microcontroller and/or a graphical processing unit to negotiate control of a switch and a bus.
US10162773B1
A system for memory management includes an incoming memory data strobe connecting a memory data interface, and a clock distribution network. The clock distribution network includes an internal clock aligned to the incoming memory data strobe. The system also includes an asynchronous clock domain that is asynchronous with the clock distribution network; and a strobe select circuit configured to align to the incoming memory data strobe. The clock distribution network is configured to propagate read data with reduced latency from the memory data interface to a second interface.
US10162770B2
Virtual machine (VM) migration in rack scale systems is disclosed. A source shared memory controller (SMC) of implementations includes a direct memory access (DMA) move engine to establish a first virtual channel (VC) over a link with a destination SMC, the destination SMC coupled to a destination node hosting a VM that is migrated to the destination node from a source node coupled to the source SMC, and transmit, via the first VC to the destination SMC, units of data corresponding to the VM and directory state metadata associated with each unit of data. The source SMC includes a demand request component to establish a second VC over the link, receive, via the second VC from the destination SMC, a demand request for one of the units of data corresponding to the VM, and transmit, via the second VC, the requested unit of data and corresponding directory state metadata.
US10162765B2
A device may receive a direct memory access request that identifies a virtual address. The device may determine whether the virtual address is within a particular range of virtual addresses. The device may selectively perform a first action or a second action based on determining whether the virtual address is within the particular range of virtual addresses. The first action may include causing a first address translation algorithm to be performed to translate the virtual address to a physical address associated with a memory device when the virtual address is not within the particular range of virtual addresses. The second action may include causing a second address translation algorithm to be performed to translate the virtual address to the physical address when the virtual address is within the particular range of virtual addresses. The second address translation algorithm may be different from the first address translation algorithm.
US10162764B2
A marking capability is used to provide an indication of whether a block of memory is backing an address translation structure of a control program being managed by a virtual machine manager. By providing the marking, the virtual machine manager may check the indication prior to making paging decisions. With this information, a hint may be provided to the hardware to be used in decisions relating to purging associated address translation structures, such as translation look-aside buffer (TLB) entries.
US10162750B2
System address reconstruction logic in accordance with one embodiment of the present description, reconstructs a system address from a channel address translated from the system address. The system address reconstruction logic includes logic configured to reconstruct one or more systems address fields as a function of the channel address, the number of memory controller target ways of the memory being equal to three, the number of bits of the granularity of interleaving of data among the memory controller target ways, the number of channels per memory controller target way, and the number of bits of the granularity of interleaving of data among the channels of a memory controller target way. Other aspects are described herein.
US10162746B2
Provided are a computer program product, system, and method for allocating additional requested storage space for a data set in a first managed space in a second managed space. A request for additional storage space is received for a requested data set stored in a first managed space in the storage. A revised amount of storage space for the requested data set comprises at least an amount of space currently allocated to the requested data set in the first managed space and the requested additional storage space. If the revised amount of storage space exceeds a value, then allocation is made of the revised amount of storage space in allocated storage space in a second managed space of the storage. The data set is stored in the allocated storage space in the second managed space.
US10162741B2
A mechanism is provided in a data processing system comprising at least one processor and at least one memory, the at least one memory comprising instructions executed by the at least one processor to cause the at least one processor to implement a user interface automation tool. The user interface automation tool executes a script to perform automation functions on user interface controls in a user interface of an application. Responsive to automation of a given user interface control failing, the user interface automation tool identifies a candidate user interface control that is the same as a user interface control expected in the script using a machine learning model. The user interface automation tool corrects the script to refer to the candidate user interface control to form a corrected script. The user interface automation tool performs a user interface function on the candidate user interface control according the corrected script.
US10162737B2
Examples disclosed herein provide tools for capturing spatial gestures performed by a user and scripting the gestures for testing an application under test. Scripts may be produced by capturing movement of extremities of a skeletal body corresponding to the user, wherein the movement is captured according to a change in coordinates of the extremities from an original position. The movement of the extremities may be matched to a predefined gesture found in a gesture database. A script may be generated from the matched predefined gesture with reference to the extremities captured and coordinates of the extremities from the original position, such that the user is emulated.
US10162730B2
A method of debugging software code in an information handling system (IHS) is disclosed. The method includes establishing communications between a debug computer and a target computer and triggering the target computer to collect and transmit a plurality of symptom and root cause (SARC) values associated with the software code. The SARC values are compared to SARC reference values associated with the software code. The method further includes determining if the SARC values meet the requirements of the SARC reference values. In response to the SARC values not meeting the requirements of the SARC reference values, at least one process associated with the SARC values that do not meet the requirements of the SARC reference values is identified. Process data corresponding to the at least one process is collected and a SARC diagnosis report is generated for the software code based on the process data.
US10162719B2
According to an embodiment, an ordering device determines a processing order of pieces of data in each computer in a multiplex system. The device includes a preliminary elector and a confidence elector. The preliminary elector is configured to generate, when a vote having the current order number, the current round number, and a nominated state is acquired from a primary computer, a vote that includes data included in the acquired vote, the current order number, a round number following the current round number, and a winning-assured state. The confidence elector is configured to determine, when a vote having the current order number, the current round number, and the winning-assured state is acquired for identical data from each of a threshold or more of the computers, data included in the acquired vote to be data to be processed at the current order number.
US10162712B2
The present invention provides systems and methods for extending media retention. Methods are provided in which a set of aging preferences are obtained. Data elements of a data set stored on storage media are evaluated against the aging preferences to determine whether each of the data elements satisfy the aging preferences. Each of the data elements that is determined to satisfy the aging preferences is aged. Aging can include freeing a portion of storage media, previously used to store a data element, for other storage usage.
US10162711B1
A method for data locality control in a deduplication system is provided. The method includes forming a fingerprint cache from a backup image corresponding to a first backup operation. The method includes removing one or more fingerprints from inclusion in the fingerprint cache, in response to the one or more fingerprints having a data segment locality, in a container, less than a threshold of data segment locality. The container has one or more data segments corresponding to the one or more fingerprints. The method includes applying the fingerprint cache, with the one or more fingerprints removed from inclusion therein, to a second backup operation, wherein at least one method operation is executed through a processor.
US10162710B2
A computer implemented method is provided. The method comprises initializing a first database image of a first database system based on a recovery image comprising committed transactions, visible uncommitted transactions, and undo logs associated with the visible uncommitted transactions, undoing the visible uncommitted transactions using the undo logs, generating redo logs from the undo logs, replaying the redo logs to create invisible uncommitted transactions, and after replaying the redo logs, replaying transaction logs received from a second database system. Related apparatus, systems, techniques and articles are also described.
US10162706B2
Embodiments of the present invention disclose a method, computer program product, and system for managing a RAID array of data storage devices. The declustered RAID array is configured to tolerate a predetermined number of failing data storage devices. The declustered RAID array of data storage devices is split into a plurality of regions, each of the plurality of regions is divided into a plurality of sets, and each of the sets of the plurality of sets utilizes a different combination of the data storage devices. The declustered RAID array provisions a plurality of LUNs from respective sets of each of the plurality of regions, and in response to a failure of one or more of the plurality of data storage devices, up to the predetermined number of failing data storage devices, the RAID array rebuilds at least one copy of each of the plurality of virtual LUNs.
US10162704B1
Techniques for encoding data storage systems using grid encoded data storage systems are described herein. Data to be stored in a data storage system is obtained and the data is stored in a grid of shards using grid encoding techniques that store the data in a combination of data shards and derived shards. Each of the shards has at least a first index corresponding to one dimension of the grid and a second index corresponding to a second dimension of the grid. Loss of a plurality of data shards can be repaired because each shard is reproducible from one or more shards with a first index that is associated with the first index of the shard and is also reproducible from one or more shards with a second index that is associated with the second index of the shard.
US10162698B2
A system and method for extensible, protective, and verifiable automated issue remediation for information technology infrastructure comprises invoking an application programming interface to obtain at least one issue object corresponding to an alert generated by a monitoring system; matching the issue object to at least one diagnosis plugin of a plurality of diagnosis plugins; obtaining a prescription object from the diagnosis plugin, the prescription object comprising a remedy; and invoking the remedy after verifying the remedy is authorized to proceed.
US10162686B2
A cache affinity and processor utilization technique efficiently load balances work in a storage input/output (I/O) stack among a plurality of processors and associated processor cores of a node. The storage I/O stack employs one or more non-blocking messaging kernel (MK) threads that execute non-blocking message handlers (i.e., non-blocking services). The technique load balances work between the processor cores sharing a last level cache (LLC) (i.e., intra-LLC processor load balancing), and load balances work between the processors having separate LLCs (i.e., inter-LLC processor load balancing). The technique may allocate a predetermined number of logical processors for use by an MK scheduler to schedule the non-blocking services within the storage I/O stack, as well as allocate a remaining number of logical processors for use by blocking services, e.g., scheduled by an operating system kernel scheduler.
US10162682B2
A processing device determines that utilization of a resource that is executing a workload meets a utilization threshold. The resource is part of multiple resources in a cluster. The processing device determines that no other resource of the cluster has available capacity for a transfer of a workload or a portion of a workload from the resource to the other resource, and determines a change to implement in a physical configuration of the cluster in view of no other resource having available capacity. The processing device sends a message over a network to implement the change, without user interaction, to the physical configuration of the cluster. The change includes adding a new physical resources to the cluster.
US10162681B2
A method, system, and program product is provided for reducing redundant validations for live operating system migration. A control point caches at least one validation inventory that is associated with a logical partition (LPAR). The control point sends the cached validation inventory to a virtualization manager upon an activation of the LPAR associated with the validation inventory. The control point invalidates the cached validation inventory upon notification from the virtualization manager that the validation inventory is changed and is no longer valid. The control point re-validates the validation inventory.
US10162669B2
Software that performs the following steps is provided: (i) running an application on a first virtual machine on a first physical server, with the application including a first plurality of independently migratable elements, including a first independently migratable element that utilizes a first resource on the first virtual machine and a second independently migratable element that utilizes a second resource on the first virtual machine; and (ii) on condition that a first migration condition exists, migrating the first independently migratable element to a second virtual machine on a second physical server, such that the first independently migratable element is able to utilize a resource that is similar to the first resource on the second virtual machine on the second physical server while the second independently migratable element remains able to utilize the second resource on the first virtual machine on the first physical server.
US10162668B2
Some embodiments of the present invention include a method comprising: accessing units of network storage that encode state data of respective virtual machines, wherein the state data for respective ones of the virtual machines are stored in distinct ones of the network storage units such that the state data for more than one virtual machine are not commingled in any one of the network storage units.
US10162661B2
Exemplary methods, apparatuses, and systems determine a list of virtual machines to be subject to a corrective action. When one or more of the listed virtual machines have dependencies upon other virtual machines, network connections, or storage devices, the determination of the list includes determining that the dependencies of the one or more virtual machines have been met. An attempt to restart or take another corrective action for the first virtual machine within the list is made. A second virtual machine that is currently deployed and running or powered off or paused in response to the corrective action for the first virtual machine is determined to be dependent upon the first virtual machine. In response to the second virtual machine's dependencies having been met by the attempt to restart or take corrective action for the first virtual machine, the second virtual machine is added to the list of virtual machines.
US10162652B2
A game apparatus has a section that stores and controls language skill of a player character, a section of locating two or more sentence items, and a section of locating an item disclosure object. A kind of language and game information are set on the sentence item, and a disclosure item, the kind of language, language level and an approach sign are set on the item disclosure object. The apparatus further has a section of reading game information that is set on the sentence item, and a section of controlling language level executes a process of improving the language skill whenever reading the sentence item.
US10162651B1
A computer system may track the user's eye gaze on a display device over time using an eye tracker. When the computer system detects a risk associated with a graphical object and determines that the user's gaze is close to the graphical object, it may display a warning message indicating the risk. The computer system may display the warning message at a location that corresponds to the graphical object associated with the risk. Furthermore, when the computer system detects a risk and determines that the user's gaze is not at the graphical object that needs the user's immediate attention, it may display a warning message near the user's current gaze to notify the user. If desired, the warning message may be hidden based on the user's gaze, such as when the user moves his gaze away from the detected risk.
US10162648B2
The invention introduces a method for dynamically selecting a booting OS (Operating System), executed by a micro-controller of an apparatus, which contains at least the following steps. The micro-controller detects a selection signal output from a selection unit, and determines which one of two ROMs (Read-Only Memories) is to be activated accordingly. After a CS (Chip Select) signal of the determined ROM is asserted, a firmware stored in the determined ROM is loaded and executed, and an OS corresponding to the firmware, which is stored in a storage device, is loaded and executed.
US10162642B2
An instruction cache and data cache used to virtualize the storage of global data and instructions used by graphics shaders. Present day hardware design stores the global data and instructions used by the shaders in a fixed amount of registers or writable control store (WCS). However, this traditional approach limits the size and the complexity of the shaders that can be supported. By virtualizing the storage of the global data and instructions, the amount of global or state memory available to the shader and the length of the shading programs are no longer constrained by the physical on-chip memory.
US10162634B2
A method, apparatus and non-transitory computer readable medium are provided for permuting data registers to a target register. Two or more data registers are concatenated to form a concatenated data register. Each data register comprises a plurality of elements. A permutation instruction which uses one of the data registers as a data input register is executed and conditionally selects an element of the data input register by comparing a portion of an element of a pattern register to an immediate match field value. The selected element of the data input register is copied to an element in a target register at a position corresponding to a position of the element of the pattern register when the portion of the element of the pattern register matches the immediate match field value. When the portion of the element of the pattern register does not match, the target register remains unchanged.
US10162631B2
A micro controller unit includes an arithmetic processing unit that executes an arithmetic processing; a peripheral circuit unit that outputs an event signal, which is a trigger for start of the arithmetic processing, based on an operation state; and a data access control unit. When an instruction to access the data designated by the first address is received from the arithmetic processing unit, the data access control unit selectively executes, depending on the event signal input from the peripheral circuit unit: a processing of instructing the data storage unit to access data designated by a first address indicating a storage location of the data on the data storage unit; and a processing of processing of converting the first address and instructing the data storage unit to access data designated by a second address, which is associated with the first address and is different from the first address.
US10162624B1
This disclosure generally relates to executing dynamically generated applications in a web browser-based shell. An exemplary method generally includes instantiating shared components in the browser-based shell, the shared components exposing a common runtime environment to widgets loaded into the browser-based shell. A first workflow definition representing a first step of a workflow is received. The first workflow definition specifies first widgets, comprising modular components that perform functions represented by the first step of the workflow and comprising a user interface definition, to be loaded into the browser-based shell. The first widgets are obtained from one or more of a remote source, a local cache, or a temporary memory and loaded into the browser-based shell. A user interface is generated according to the first workflow definition to exposes the function to a user which, when invoked, initiates a transition to a second step of the workflow.
US10162609B2
A computer-implemented method for creating an object for data access is provided. The computer-implemented method includes defining a function-expression in source code using an object-oriented programming language. The defined function-expression is exposed in a graphical user interface of a development tool used to create the object. A selection of at least one field among a list of available fields for data access is received. The defined function-expression is included in the list of available fields. An integrated development environment is also provided.
US10162608B2
The present disclosure relates to a system for providing a multi-technology visual integrated data management and analytics development and deployment environment. In an embodiment, the system is configured to generate executable code suitable to carry out a data analytics request using a first software platform, migrate executable code for the first software platform to a second software platform, and cause executable code to be processed on the first or second software platform to perform the data analytics request.
US10162599B1
In some applications, such as randomization and cryptography, remainder computation for a number is required. The remainder computation is also used in modulo arithmetic. The remainder computation can be simplified when the divisor belongs to a certain class of numbers. A method and apparatus are disclosed that enable low complexity implementation of remainder computation of any number when the divisor belongs to a type of numbers that can be represented as 2k+1.
US10162598B2
A technique relates to flash-optimized data layout of a dataset for queries. Selection columns are stored in flash memory according to a selection optimized layout, where the selection optimized layout is configured to optimize predicate matching and data skipping. The selection optimized layout, for each selection column, is formed by storing a selection column dictionary filled with unique data values in a given selection column, where the unique data values are stored in sorted order in the selection column dictionary. Row position designations are stored corresponding to each row position that the unique data values are present within the given selection column, without duplicating storage of any of the unique data values that occur more than once in the given selection column.
US10162591B2
A coiled coil geometry of modular concave LED/OLED panels or “tiles” can effectively display a simulated barreling wave. The structure of the coiled coil LED/OLED modules allows one or more users/participants to stand on and/or sit in a motion or non-motion seating platform to observe the simulation.
US10162587B2
A non-transitory computer-readable recording medium storing computer-readable instructions which causes an information processing terminal to transmit first request information requesting an image processing apparatus to transmit first information, receive the first information, as a response to the first request information, from the image processing apparatus, determine whether a set value of the received first information is the first value or the second value. When the first information is set to the first value, the instructions further cause the information processing terminal to transmit second request information requesting the image processing apparatus to transmit the second information, and receive the second information, as a response to the second request information, from the image processing apparatus. When the first information is set to the second value, the instructions do not cause the information processing terminal to transmit the second request information and to receive the second information.
US10162584B1
A printing system includes: an information processing terminal; a print server; a printing device; and an authentication server, wherein the information processing terminal uses a server printer driver for issuing a printing instruction, the printing device transmits authentication information to the print server, the print server requests the authentication server to perform user authentication, and the printing device performs printing, the information processing terminal including: a hardware processor that creates a second print job; and a second print job transmitter that transmits the second print job to the printing device, the printing device including: a second print job receiver that receives the second print job from the information processing terminal; the hardware processor that: recognizes that the printing system is in a non-server transit state; and instructs directly the authentication server to perform the user authentication; and a printer that performs printing based on the second print job.
US10162567B2
A computer system includes a first storage control module and at least one server module. The first storage control module includes plural storage processors. Each server module includes a server processor and a server I/F connected to the server processor and at least two of the plurality of storage processors. The sever I/F of an issuance server which is any one of the at least one server module specifies the storage processor by referring to sorting information in which identification information of the issuance server of an I/O request issued by the server processor of the issuance server, identification information of a destination storage area of the I/O request, and identification information of the storage processor in charge of the destination storage area are correlated with each other, and sends a command based on the I/O request to the specified storage processor.
US10162558B2
Direct data transfer between devices having a shared bus may be implemented with reduced involvement from a controller associated with the devices. A controller, a source memory device, and a target memory device may be coupled with a shared bus. The controller may identify a source address at the source memory device for data to be transferred to the target memory device. The controller also may identify a target address in the target memory device, and initiate a data transfer directly from the source to the target through a command that is received at both the source and the target memory device. In response to the command, the source memory device may read data out to the bus, and the target memory may read the data from the bus and store the data starting at the target address without further commands from the controller.
US10162554B2
A memory module has a logic including a programming register, a deduplication ratio control logic, and a deduplication engine. The programming register stores a maximum deduplication ratio of the memory module. The control logic is configured to control a deduplication ratio of the memory module according to the maximum deduplication ratio. The deduplication ratio is programmable by the host computer.
US10162545B2
An adaptive logical storage element comprises a plurality of solid-state storage elements accessible in parallel. The logical storage element includes logical storage units, which may include logical page, logical storage divisions (erase blocks), and so on. Each logical storage unit comprises a plurality of physical storage units. A logical storage unit may include one or more physical storage units that are out-of-service (OOS). The OOS status of logical storage units is tracked by OOS metadata. When data is stored on the logical storage element, padding data is provided to physical storage units that are OOS, and valid and/or parity data is provided to in-service physical storage units. A write data pipeline accesses the OOS metadata to insert padding data, and a read data pipeline accesses the OOS metadata to strip padding data.
US10162536B2
A storage apparatus includes a semiconductor storage device, and a storage controller coupled to the semiconductor storage device, and which stores data to a logical storage area provided by the semiconductor storage device. The semiconductor storage device includes one or more non-volatile semiconductor storage media, and a medium controller coupled to the semiconductor storage media. The medium controller compresses data stored in the logical storage area, and stores the compressed data in the semiconductor storage medium. The size of a logical address space of the logical storage area is larger than a total of the sizes of physical address spaces of the semiconductor storage media.
US10162529B2
A system for dynamically utilizing data storage comprises a processor and a memory. The processor is configured to determine whether a data storage criterion is satisfied; and, in the event that the data storage criterion is satisfied: determine a new archiving threshold based on a target data storage usage level; and set the archiving threshold. The memory is coupled to the processor and is configured to provide the processor with instructions.
US10162527B2
A system according to one embodiment includes a processor and logic integrated with and/or executable by the processor. The logic is configured to cause the processor to store hierarchically-organized global configuration information for each node and each tape library resource in a storage cluster to at least one memory accessible by each node of the storage cluster. The storage cluster includes at least one tape library. Also, the logic is configured to cause the processor to migrate data to and/or recall data from a tape cartridge pool within a tape library, using the hierarchically-organized global configuration information and via a node which has access to the tape cartridge pool, in response to receiving a migration and/or recall request at any node of the storage cluster. Other systems, methods, and computer program products for management of data and resources in a tiered data storage system are described in more embodiments.
US10162525B2
Methods, systems, and computer program products for receiving a memory access request, the memory access request including a virtual memory address; locating a page entry in a page entry structure, the page entry corresponding to the virtual memory address; identifying that a page corresponding to the page entry includes a sub-page, the sub-page included within a subset of a memory space allocated to the page; determining a page frame number corresponding to the sub-page and an offset corresponding to the sub-page; and accessing the offset within the sub-page.
US10162521B2
A Data Storage Device (DSD) is in communication with a plurality of sensing devices. Data is received for storage in the DSD from a sensing device of the plurality of sensing devices. The received data is associated with at least one storage hint assigned to the sensing device. A media region of the DSD is selected from a plurality of media regions for storing the received data based on the at least one storage hint and at least one characteristic of the media region.
US10162514B2
A system and method for an interactive avionics display system integrates a large-format primary avionics display, a secondary avionics display capable of mirroring the display of electronic flight bag mobile devices, a format selector panel, and a keyboard panel. Background displays and foreground multifunction windows generated by the display system house applications and display relevant avionics data. The multifunction windows can be resized or repositioned on the display surface using finger contacts and gestures. Format selector panels include control selectors corresponding to the multifunction windows, the control selectors responsive to finger contact with the format selector panels or the corresponding multifunction windows. Keyboard panels provide touch-sensitive radio and communications controls as well as an alphanumeric keyboard responsive to finger contact with text fields generated by the display.
US10162510B2
An apparatus including: a display including a central portion and a curved side portion; a memory storing pages of content; and a display controller configured to control simultaneously the central portion of the display to display at least a portion of a first page of content and the curved side portion of the display to display additional information not forming part of the first page of content.
US10162507B2
A display control apparatus includes an acquiring unit that acquires object information to be displayed on a screen; a storing unit that stores the acquired object information, time information, and a priority related to a display of an object corresponding to the acquired object information while associating the acquired object information, the time information, and the priority for each acquired object information; and a display controlling unit that controls a display position of the object based on the time information and the priority associated with the object information when the object is displayed on a screen.
US10162504B2
The different advantageous embodiments provide a computer implemented method, apparatus, and computer program product for generating a display of magnified information. A selection is received of an area of a chart on a display device to form a selected area through a user input device. Coordinates are identified for the selected area. A category assigned to the selected area is identified using the coordinates identified. Related areas of the chart are identified using the category identified. The selected area and the related areas are compiled to form display information and the display information is displayed on the display device having a selected size.
US10162498B2
In some embodiments, a processor accesses electronic content that includes multiple selectable objects that are renderable in a graphical interface. The processor generates multiple selection areas respectively associated with the selectable objects. An input to the graphical interface received within each selection area selects an associated selectable object. Generating the selection areas includes generating a boundary around at least one of the selectable objects. Any point within the boundary is closer to the associated selectable object than any other selectable object. Generating the selection areas also includes clipping the boundary to define the selection area for the selectable object. The processor adds the selection areas to a document object model associated with the electronic content. The document object model is usable for rendering the graphical interface with the selectable objects and identifying the selection areas.
US10162495B2
Customization features for providing users with the ability to customize various aspects of a vehicle management system are described. These customization features can include functionality for generating custom reports based on vehicle parameters, including diagnostic codes. The customization features can also include features for customizing alerts based on vehicle parameters and features for customizing nomenclature in the vehicle management system.
US10162489B2
A mobile terminal and a method for controlling the same are disclosed. The mobile terminal includes a display and a controller configured to display at least one piece of video content on the display, to extract at least one text from at least one of an image and sound included in at least a portion of the video content and to display the at least one text on at least one specific position of the display, wherein the at least one specific position is related to at least one point of the video content, from which the at least one text is extracted. According to the present invention, video content can be manipulated more conveniently by displaying images and sound included in the video content as text.
US10162485B2
A display apparatus includes a display, a function setting circuit, a switching control circuit, and a simple menu creation control circuit. The simple menu creation control circuit creates, when it is determined by the switching control circuit that a number of times of selection is greater than or equal to a set number or an elapsed time is greater than or equal to a set time, a first simple menu for use in display on the display, the first simple menu being obtained by eliminating, from the plurality of operation menu items, an operation menu item corresponding to a function whose number of times of selection by a user is greater than or equal to a set number.
US10162480B2
There is provided an information processing apparatus including an operation surface configured to receive touch inputs, and a sensor unit configured to detect at least one right-side touch input from a manipulation by a user of the operation surface within a first operational area of the operation surface, and at least one left-side touch input from a manipulation by the user of the operation surface within a second operational area of the operation surface, wherein the first operational area and the second operational area of the operation surface are mapped to a graphical user interface (GUI) area of a display device.
US10162476B2
A computer-implemented method displays an assembly of digitally modeled objects in a three-dimensional scene, by the steps of: defining at least one object of the assembly as being revealable; generating a graphical representation of the assembly wherein said revealable object is located at least partially behind at least another object, called hiding object, and displaying said graphical representation; using a graphical tool selecting a region of said graphical representation of the assembly, called a revealing zone; and rendering a three-dimensional scene comprising a three-dimensional representation of the assembly wherein a portion of the revealable object located behind the hiding object and comprised within the revealing zone is shown by transparency through said hiding object. A computer program product, a non-volatile computer-readable data-storage medium and a Computer Aided Design system for carrying out such a method.
US10162469B2
[Object] In a touch screen in which an electrode portion is formed on a base film, a pattern of the electrode portion is made less visible. [Solution] A touch screen 1 includes a first base film 11, a first transparent electrode 15, a second base film 13, a second transparent electrode 17, and a second intermediate base film 21. The first transparent electrode 15 is formed on the first base film 11. The second base film 13 is placed to face the first base film 11. The second transparent electrode 17 is formed on the second base film 13. The second intermediate base film 21 has a retardation value of 3000 nm or more and is placed so that a contraction direction thereof and contraction directions of the first base film 11 and the second base film 13 are matched.
US10162468B2
When at least one external object approaches or touches a touch sensor, profiles in a scanning signal corresponding to each external object will appear. The smallest value between the profiles corresponding to a first and a second external object is designated as a division value when the profiles corresponding to the first and the second external objects overlap. The overlapping profiles can be divided into the portion of the first external object and the portion of the second external object, respectively.
US10162466B2
A portable device includes a display, a touch panel including at least one curved area, and at least one processor. The at least one processor is configured to, when a touched position on the touch panel is within the curved area, determine a direction from which a touched position indicator has approached the curved area, and modify the touched position based on the determined direction.
US10162456B2
Touch events can be predicted relative to a visual display by maintaining a database of aggregated touch event history data relative to the visual display and from a plurality of touch screen devices. The database can be queried according to a set of input parameters defining an environment for use of the visual display. The results from the querying of the database can be analyzed to predict a set of touch events within the environment and based upon inferences obtained from the results. A representation of the set of touch events can be displayed along with the visual display.
US10162448B1
Apparatuses and a computer-readable media are provided to: display a list of messages via an interface; detect a pressure being applied to the touch screen on at least one of the messages of the list; in the event that the magnitude of the pressure being applied to the touch screen on the at least one message is less than a first magnitude threshold, display the at least one message after a cessation of the pressure has been detected; in the event that the magnitude of the pressure being applied to the touch screen on the at least one message is greater than the first magnitude threshold and is less than a second magnitude threshold: based on an increase in the magnitude of the pressure being applied to the touch screen on the at least one message: increase a blurring of at least a portion of the interface other than the at least one message, and increase a magnification of at least a portion of the at least one message, such that the at least portion of the interface appears to be increasing in depth as compared to the at least portion of the at least one message, and based on a decrease in the magnitude of the pressure being applied to the touch screen on the at least one message: decrease the blurring of the at least portion of the interface other than the at least one message, and decrease the magnification of the at least portion of the at least one message, such that the at least portion of the interface appears to be decreasing in depth as compared to the at least portion of the at least one message.
US10162444B2
A force-sensitive device for electronic device. The force inputs may be detected by measuring changes in capacitance, as measured by surface flex of a device having a flexible touchable surface, causing flex at a compressible gap within the device. A capacitive sensor responsive to changes in distance across the compressible gap. The sensor can be positioned above or below, or within, a display element, and above or below, or within, a backlight unit. The device can respond to bending, twisting, or other deformation, to adjust those zero force measurements. The device can use measure of surface flux that appear at positions on the surface not directly the subject of applied force, such as when the user presses on a part of the frame or a surface without capacitive sensors.
US10162443B2
Providing a virtual keyboard interaction is disclosed. An indicator identifying a force intensity of a touch input provided on a touch input surface is received. It is determined that the touch input is associated with a virtual keyboard. A virtual keyboard interaction is provided based at least in part on the indicator identifying the force intensity of the touch input.
US10162442B2
A compliant support for a display device is described. In one or more implementations, an apparatus includes an external enclosure configured to assume a mobile computing device configuration and one or more computing components secured by and disposed within the external enclosure. The one or more computing components are configured to perform one or more operations that are specified by software. A display device is secured to the external enclosure such that the display device is viewable by a user, the display device supporting touchscreen functionality. A compliant support is disposed between the one or more computing components and the display device, the compliant support configured to reduce deflection of the display device by compression of the compliant support, the deflection caused in response to contact against a surface of the display device.
US10162429B2
A gesture-enabled keyboard and method are defined. The gesture-enabled keyboard includes a keyboard housing including one or more keyboard keys for typing and a pair of stereo camera sensors mounted within the keyboard housing, a field of view of the pair of stereo camera sensors projecting substantially perpendicularly to the plane of the keyboard housing. A background of the field of view is updated when one or more alternative input devices are in use. A gesture region including a plurality of interaction zones and a virtual membrane defining a region of transition from one of the plurality of interaction zones to another of the plurality of interaction zones is defined within the field of view of the pair of stereo camera sensors. Gesture interaction is enabled when one or more gesture objects are positioned within the gesture region, and when one or more alternative input devices are not in use.
US10162428B2
A KVM (K: keyboard, V: Video, M: Mouse) switch connectable between a plurality of computers and a display, including: a plurality of input terminals that input analog image signals from the computers, respectively; a storage that stores an adjustment value that adjusts an image quality of each of the analog image signals for each input terminal; a processor that selects any one of the plurality of input terminals in accordance with an operation of an keyboard; and an adjustment circuit that adjusts the image quality of an analog image signal input to the selected input terminal based on the adjustment value corresponding to the selected input terminal.
US10162425B2
An input device includes a touch panel incorporating a switch electrode region, and an actuator. The switch electrode region includes a switch electrode and a ground electrode disposed side by side with the switch electrode. The actuator includes a push button having an operation surface, an elastic body, a conductor, and a facing surface. The conductor faces the switch electrode region and is separated from the switch and ground electrodes. The conductor moves in line with a press put on the push button such that a capacitance value between the conductor and each of the switch and ground electrodes changes in response to a distance between the conductor and the switch electrode.
US10162419B2
A method includes detecting a query gesture and actuating, in response to the query gesture, an actuator to provide tactile feedback including information associated with the query gesture. The query gesture may be detected on a touch-sensitive display of a portable electronic device.
US10162418B2
An input device may include a wire element and a moveable substrate coupled to the wire element. The moveable substrate may include various wire alignment features. The input device may further include an input surface disposed above the moveable substrate. The input device may further include various sensor electrodes coupled to the input surface. The input device may further include a haptic actuator coupled to the moveable substrate. The haptic actuator may displace the moveable substrate in a direction substantially parallel to a plane of the input surface. The wire element may return the moveable substrate to an original position. The wire alignment features may allow, in response to an applied force by the haptic actuator and to the moveable substrate, a displacement of the moveable substrate in the direction that is substantially parallel to the plane of the input surface.
US10162417B2
A method of tuning a haptic actuator that includes a housing having an initial ferromagnetic mass, at least one coil carried by the housing, and a field member movable within the housing responsive to the at least one coil, wherein the haptic actuator operative as a resonator and has an initial quality (Q) factor, may include measuring the initial Q factor of the haptic actuator. The method may include determining a desired ferromagnetic mass for the housing to tune the initial Q factor to a desired Q factor. The method may also include changing the initial ferromagnetic mass of the housing to the desired ferromagnetic mass. Another embodiment changes the ferromagnetic mass of the field member.
US10162410B1
A head-tracking system for dismounted users comprises an inertial georeferenced head tracker (IGHT) having a time-cumulative drift error, an azimuth-referenced head-tracker (ARHT), and a controller. The ARHT comprises a data link with an angle of arrival antenna, differential global position satellite receivers, and a processor configured to determine the head position of the user and initialize the IGHT. The controller may compare a current drift error of the IGHT with a predetermined drift error threshold. If the current drift error is below the predetermined drift error threshold, the IGHT data may accurately represent the head position of the user. If the current drift error is above the predetermined drift error threshold, the IGHT may be updated with the ARHT data to accurately represent the head position of the user.
US10162408B2
A head mounted display for supporting improvement in an act of moving a body is provided. The head mounted display includes image display unit that transmits external scenery therethrough and forms an image, a body motion detection unit that detects motions of a body of a user and at least a part of a tool bundled with the body, a model moving image acquisition unit that accesses a model moving image storage unit which stores, as a model moving image, a moving image showing a motion of the body, used as a reference of the act and stores the model moving image for each type of act, and acquires one or a plurality of model moving images corresponding to a detection result from the body motion detection unit, and a display control unit that causes the image display unit to form the acquired model moving image.
US10162399B2
In some examples, a power adapter includes a voltage regulator, first and second resistors, a switch to alternately connect the first and second resistors to a signal node coupled to a load circuit external of the power adapter, and a voltage controller to control the switch to set a first mode of operation, and responsive to the switch setting the first mode of operation, determine a power requirement of the load circuit, and control the voltage regulator to provide a supply voltage to a power node in accordance with the power requirement of the load circuit, and control the switch to set the second mode of operation that causes the load circuit to determine a power rating of the power adapter and to operate a load of the load circuit according to the power rating of the power adapter.
US10162398B2
A method for performing power management in an electronic system and associated apparatus are provided, where the method is applied to at least one electronic device of a plurality of electronic devices of the electronic system. Based on the method, the electronic system utilizes a control electronic device within the plurality of electronic devices to send a first turning on signal to a first electronic device within the plurality of electronic devices to trigger the first electronic device to turn on, wherein the first electronic device is coupled to the control electronic device. The electronic system utilizes the first electronic device to send a second turning on signal to a second electronic device within the plurality of electronic devices to trigger the second electronic device to turn on, wherein the second electronic device is coupled to the control electronic device through the first electronic device.
US10162395B2
The description relates to devices, such as computing devices. One example can include a sandwich structured composite housing. The example can also include a set of electronic components positioned over the sandwich structured composite housing. The set of electronic components can have a profile against the sandwich structured composite housing. The sandwich structured composite housing can have a corresponding negative profile.
US10162390B2
The described embodiments relate to an electronic assembly that includes multiple varied electrical components. In some embodiments, the electronic assembly can include electrical components susceptible to electromagnetic interference (EMI). In one particular embodiment, an antenna can be positioned along an exterior surface of an enclosure of the electronic assembly and another electrical component can be disposed within the enclosure. When the other electrical component is a speaker component, a port or opening for emitting audio output can be protected from EMI by surrounding the port with a conductive gasket that includes a closed cell foam substrate wrapped in an electrically conductive fabric. In some embodiments, the closed cell foam substrate defines a number of perforations that are plated with an electrically conductive material.
US10162387B2
A rollable display device is provided. The rollable display device includes first and second bodies, a display, a roller supported in the first body to be rotatable, to which one end portion of the display in a length direction of the display is fixed and around an outer circumference of which the display is wound, and a support member a plurality of segmented links connected to pivot around a hinge shaft perpendicular to an image display surface, the support member being accommodated in an accommodation unit provided in the first body. As the first body is separated from the second body, the display is unwound from the roller and is unrolled outward from the first body to expand in the length direction, and the support member is unrolled outward from the first body in the length direction to support a rear surface of the display.
US10162384B2
A display device includes: a display panel including a display area having a circular shape; and a cover window on the display panel, wherein the cover window includes: a center portion covering a center area of the display area; and an edge portion covering an edge area of the display area, and the edge portion is chamfered.
US10162380B2
A method for synchronizing a plurality of components that are networked via a plurality of high speed switches, the method includes frequency-locking to a master clock component clocks of the plurality of components, and synchronizing to a master counter, driven by the master clock, component counters of the plurality of components, so that the frequency-locked component clocks drive the component counters in synchrony with the master counter.
US10162378B1
Described is a neuromorphic processor for signal denoising and separation. The neuromorphic processor generates delay-embedded mixture signals from an input mixture of pulses. Using a reservoir computer, the delay-embedded mixture signals are mapped to reservoir states of a dynamical reservoir having output layer weights. The output layer weights are adapted based on short-time linear prediction, and a denoised output of the mixture of input signals us generated. The denoised output is filtered through a set of adaptable finite impulse response (FIR) filters to extract a set of separated narrowband pulses.
US10162377B2
A reference voltage generator is disclosed that may provide a plurality of reference voltages. A reference voltage generator may include a voltage divider, a multiplexer coupled to the voltage divider, an operational amplifier that may receive a voltage from the multiplexer, and a plurality of resistors that may receive an output from the operational amplifier. The reference voltages may be provided from output terminals coupled to the resistors. A reference voltage generator may include a voltage divider, two multiplexers coupled to the voltage divider, an operational amplifier coupled to each multiplexer, and a plurality of resistors coupled between the outputs of the two operational amplifiers. Reference voltages may be provided from output terminals coupled to the resistors.
US10162373B1
Various aspects provide for detecting voltage droops. For example, a system can include a voltage calibrator component and a comparator component. The voltage calibrator component can convert a first supply voltage associated with a power distribution network of an integrated circuit to a second supply voltage via a resistance ladder circuit. The comparator component can generate a comparison output signal in response to a determination that a comparison between the second supply voltage and a reference voltage satisfies a defined criterion.
US10162367B2
An unmanned aircraft includes a forward propulsion system comprising one or more forward thrust engines and one or more corresponding rotors coupled to the forward thrust engines; a vertical propulsion system comprising one or more vertical thrust engines and one or more corresponding rotors coupled to the vertical thrust engines; and a pitch angle and throttle control system, comprising a processor configured to receive a first pitch angle command; and generate a second pitch angle command and a forward thrust engine throttle command based on a bounded pitch angle for the aircraft.
US10162363B1
A system and method is provided for identifying an object along a road, where the object may be represented by a bounding box, and projecting a set of obstacle points within the bounding box corresponding to the identified object. In one aspect, a two-dimensional plane oriented perpendicular to a direction of the movement of the vehicle may be identified. In another aspect, the areas of the plane that may be occupied based on the set of obstacle points may be determined to generate a contour of the identified object. Thereafter, the height profiles of the identified object and the vehicle may be determined and identified, respectively. Based on the height profiles, a minimum clearance may be determined.
US10162360B2
A vehicle includes at least one image capture device and a user display configured to display images receive from the at least one image capture device. The vehicle also includes a controller programmed to generate a user prompt to set a home vehicle position in response the vehicle entering a first parked state. The controller is also programmed to store at least one reference image indicative of an area in a vicinity of the vehicle corresponding to the home vehicle position. The controller is further programmed to collect a current image corresponding to a current vehicle position in response to a subsequent approach toward the vicinity, and compare the current image to the reference image. The controller is further programmed to generate a user display depicting the vicinity, the current vehicle position, and the home vehicle position.
US10162343B2
A process for performing localized corrective actions to structure of an electronic device is described. The structure may include a mating surface configured to receive another structure such that the two structures may be, for example, adhesively bonded together. The localized corrective actions are configured not to improve the mating surface but to also prevent light within the electronic device from escaping in undesired areas of the electronic device. In some embodiments, the corrective action includes using a removal tool to remove identified portions of the surface. In other embodiments, the corrective action includes using a different tool to add material identified portions of the surface. The identified means may include an automated inspection system.
US10162324B2
A method for manipulating a first function of a control program of an electronic control device, using a second function. The control program is processed using a first calculation kernel of a processor, and the second function is processed by a second calculation kernel during the processing of the control program. The first function assigns a first value to a variable and writes the first value to the storage address of the variable at a first time. The second function assigns a second value to the variable, which value is written to the storage address of the variable at a second time, wherein the second value written by the first function is overwritten. At a third time, the control program reads the second value from the storage address of the variable. A control entity coordinates the times at which the storage address of the variable is accessed.
US10162316B2
A controllable device, such as a set top box, responds to a transmission received from a one of a plurality of controlling devices of differing capabilities by entering into a one of a plurality of operating modes wherein the one of the plurality of operating modes entered into corresponds to the capabilities of the controlling device from which the transmission originated.
US10162315B2
Methods, systems, and non-transitory, computer-readable medium are disclosed to enable a user to configure a process control system. A graphical programming user interface is described for generating coded native control components instantiated from typical and adapter components selected from a library of templates including respective control functions and associated logical expressions. In various embodiments, typical components represent a common core control process or function that is used among one or more other plant equipment devices in the process control system. In addition, various embodiments of the adapter components include one or more parameters that may be changed by a user in conjunction with the logical expressions and/or defined in terms of natural language expressions. As a result, the typical component and the adapter component are instantiated to provide a native control component that provides functionality with respect to one or more control loops within a process control system.
US10162313B2
An equipment isolation system (10) for remotely isolating equipment (20, 21, 210, 250) in a plant comprising equipment (20, 21, 210, 250) energisable by an energy source and a control system (50) for controlling operation of said equipment (20, 21, 210, 250) and isolation of said equipment from said energy source to an isolated state by an operator, wherein said control system (50, 260, 700) includes an identification device (790) for an operator to provide operator identification data; and a processor for comparing said operator identification data with stored identification data (261) for operators authorised to use the equipment isolation system (10) wherein said control system (50, 260, 700) is configured to enable use of the equipment isolation system (10) by said operator only where the processor matches operator identification data provided to the identification device (790) and said stored identification data (261).
US10162310B2
A method of forming a decorative surface on a micromechanical timepiece part including a silicon-based substrate, including at least one step a) of forming pores (2) on the surface of the silicon-based substrate over a zone of the silicon-based substrate which corresponds to the decorative surface to be formed, the pores being designed to open out at the external surface of the micromechanical timepiece part. A micromechanical timepiece part including a silicon-based substrate, and having, over at least one zone of the silicon-based substrate, pores which are formed in the zone of the silicon-based substrate and open out at the external surface of the micromechanical timepiece part in order to form a decorative surface over the zone.
US10162308B2
Disclosed herein are methods and systems for real-time holographic augmented reality image processing. The processing includes the steps of receiving, at a computer device and from an image capturing component, real-time image data; extracting one or more objects or a scene from the real-time image data based on results from real-time adaptive learning and one or more object/scene extraction parameters; extracting one or more human objects from the real-time image data based on results from real-time adaptive human learning and one or more human extraction parameters, receiving augmented reality (AR) input data; and creating holographic AR image data by projecting, for each image, the extracted object or scene, the extracted human object, and the AR input data using a multi-layered mechanism based on projection parameters. The real-time adaptive learning comprises object learning, object recognition, object segmentation, scene learning, scene recognition, scene segmentation, or a combination thereof. The real-time adaptive human learning comprises human characteristic learning, human recognition, human segmentation, human body movement tracking, or a combination thereof.
US10162304B2
A process cartridge is detachably mountable to a main assembly of an electrophotographic image forming apparatus. The cartridge includes an electrophotographic photosensitive drum, a developing roller, a drum unit containing the drum, a developing unit containing the roller and being movable so the roller contacts and is spaced from the drum, and a first force receiver receiving a force from a main-assembly first force applier by movement of a door from open to closed positions when mounting the cartridge and a second force receiver movable from a stand-by position by movement of the first force receiver by a force received from the first force applier. The second force receiver takes a projected position receiving a force from the second force applier to move the developing unit so the roller moves out of contact with the drum, the projected position being higher than the stand-by position.
US10162301B2
An image forming apparatus includes a developing device including a photosensitive unit having a photoreceptor and a developing unit having a developing roller; a light scanning unit including a light source to generate light to form an electrostatic latent image on the photoreceptor and a window through which the light is transmitted; a shutter unit to open and close the window; a plurality of pressing units to press the developing unit to cause the developing roller separated from the photoreceptor to contact the photoreceptor and cause the shutter unit to open and close the window; and an operating unit connected to the plurality of pressing units. The operating unit is movable between an operating position to generate a pressing force by the plurality of pressing units to press the developing unit and the shutter unit and a standby position to release the pressing force.
US10162272B2
A substrate has a plurality of overlay gratings formed thereon by a lithographic process. Each overlay grating has a known overlay bias. The values of overlay bias include for example two values in a region centered on zero and two values in a region centered on P/2, where P is the pitch of the gratings. Overlay is calculated from asymmetry measurements for the gratings using knowledge of the different overlay bias values, each of the overall asymmetry measurements being weighted by a corresponding weight factor. Each one of the weight factors represents a measure of feature asymmetry within the respective overlay grating. The calculation is used to improve subsequent performance of the measurement process, and/or the lithographic process. Some of the asymmetry measurements may additionally be weighted by a second weight factor in order to eliminate or reduce the contribution of phase asymmetry to the overlay.
US10162271B2
In a dark-field metrology method using a small target, a characteristic of an image of the target, obtained using a single diffraction order, is determined by fitting a combination fit function to the measured image. The combination fit function includes terms selected to represent aspects of the physical sensor and the target. Some coefficients of the combination fit function are determined based on parameters of the measurement process and/or target. In an embodiment the combination fit function includes jinc functions representing the point spread function of a pupil stop in the imaging system.
US10162268B2
Implementations disclosed herein generally relate to a light pipe, or kaleido, for homogenizing light such that the light is uniform once the light exits the light pipe. By reflecting the light inside the light pipe, light uniformity is increased. In one implementation, a light pipe for an image projection apparatus is provided. The light pipe comprises an elongated rectangular body having a refractive index that provides total internal reflection within the elongated rectangular body. The elongated rectangular body has an input face for accepting light into the elongated rectangular body. The input face disposed substantially orthogonal to a longitudinal axis of the elongated rectangular body. The elongated rectangular body has an output face for releasing light from the elongated rectangular body. The output face is disposed substantially orthogonal to the longitudinal axis. The elongated rectangular body has a twist along the longitudinal axis.
US10162267B2
The invention relates to a projection exposure apparatus for semiconductor lithography, comprising an illumination system for illuminating a mask arranged on a movable mask stage, and comprising a projection lens for imaging the mask onto a semiconductor substrate, wherein at least one means is present for at least partly decoupling at least parts of the illumination system and/or of the projection lens from the influence of pressure fluctuations in the medium surrounding the projection lens or the illuminated system, the pressure fluctuations being attributed to movements of the mask stage during the operation of the apparatus.
US10162266B2
Provided are methods of trimming a photoresist pattern. The methods comprise: (a) providing a semiconductor substrate; (b) forming a photoresist pattern on the substrate, wherein the photoresist pattern is formed from a chemically amplified photoresist composition comprising: a matrix polymer comprising an acid labile group; a photoacid generator; and a solvent; (c) coating a photoresist trimming composition on the substrate over the photoresist pattern, wherein the trimming composition comprises: a matrix polymer, an aromatic acid that is free of fluorine; and a solvent; (d) heating the coated substrate, thereby causing a change in polarity of the photoresist matrix polymer in a surface region of the photoresist pattern; and (e) contacting the photoresist pattern with a rinsing agent to remove the surface region of the photoresist pattern, thereby forming a trimmed photoresist pattern. The methods find particular applicability in the manufacture of semiconductor devices.
